scholarly journals Tuneable Current Mode RMS Detector

2015 ◽  
Vol 66 (1) ◽  
pp. 11-18
Author(s):  
Predrag B. Petrović
Keyword(s):  
Signal Processing ◽  
Theoretical Analysis ◽  
Integrated Circuits ◽  
Current Mode ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Current Conveyors ◽  
Band Limited ◽  
Controlled Current Conveyors ◽  
Good Agreement

Abstract A new realization of RMS detector, employing two CCCIIs (controlled current conveyors), metal-oxide-semiconductor transistors and single grounded capacitor is present in this paper, without any external resistors and components matching requirements. The proposed circuit can be applied in measuring the RMS value of periodic, band-limited signals. The proposed circuit is very appropriate to further develop into integrated circuits. The errors related to the signal processing and errors bound were investigated and provided. To verify the theoretical analysis, the circuit PSpice simulations have also been included, showing good agreement with the theory.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

scholarly journals A comparative study of hole and electron inversion layer quantization in MOS structures

2010 ◽  
Vol 7 (2) ◽  
pp. 185-193 ◽  
Author(s):  
Amit Chaudhry ◽  
Nath Roy
Keyword(s):  
Charge Density ◽  
Marked Decrease ◽  
Inversion Layer ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Capacitance ◽  
Variation Approach ◽  
Inversion Charge ◽  
Mos Structures ◽  
Good Agreement

In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Octahedral-Structured Gigantic Precipitates as the Origin of Gate-Oxide Defects in Metal-Oxide-Semiconductor Large-Scale-Integrated Circuits

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 812-817 ◽  
Author(s):  
Manabu Itsumi ◽  
Hideo Akiya ◽  
Takemi Ueki ◽  
Masato Tomita ◽  
Masataka Yamawaki
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Large Scale ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Oxide Defects

Fundamentals of SiC-Based Device Processing

MRS Bulletin ◽  
1997 ◽  
Vol 22 (3) ◽  
pp. 42-49 ◽  
Author(s):  
M.R. Melloch ◽  
J.A. Cooper ◽  
D.J. Larkin
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Oxidation Rate ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Processing Technology ◽  
Oxide Semiconductor ◽  
Processing Technologies ◽  
Oxidation Rates ◽  
Polysilicon Gate

Since the commercial availability of SiC substrates in 1990, SiC processing technology has advanced rapidly. There have been demonstrations of monolithic digital and analogue integrated circuits, complementary metal-oxide-semiconductor (CMOS) analog integrated circuits, nonvolatile random-access memories, self-aligned polysilicon-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), and buried-channel polysilicon-gate charge-coupled devices (CCDs). In this article, we review processing technologies for SiC.OxidationA beneficial feature of SiC processing technology is that SiC can be thermally oxidized to form SiO2. When a thermal oxide of thickness x is grown, 0.5x of the SiC surface is consumed, and the excess carbon leaves the sample as CO. Shown in Figure 1 are the oxide thicknesses as a function of time for the Si-face and the C-face of 6H-SiC, and for Si. The oxidation rates are considerably lower for SiC than for Si. The oxidation rate of the C-face of 6H-SiC is considerably greater than that of the Si-face. Hornetz et al. have shown that the reason for the slower oxidation rate of the Si-face is due to a 1-nm Si4C4−xO2 (x < 2) layer that forms between the SiC and the SiO2 during oxidation of the Si-face. When oxidizing the Si-face, the Si atoms oxidize first, which inhibits the oxidation of the underlying C atoms that are 0.063 nm below the Si atoms. When oxidizing the C-face, the C atoms readily oxidize first to form CO, with no formation of the Si4C4−xO2 layer for temperatures above 1000°C.

Experimental Basis and Design of a New Cochlear Prosthesis System

1987 ◽  
Vol 96 (1_suppl) ◽  
pp. 76-79
Author(s):  
J. Génin ◽  
R. Charachon
Keyword(s):  
Theoretical Model ◽  
Integrated Circuits ◽  
Cochlear Implant ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Technology ◽  
Experimental Basis ◽  
Cochlear Prosthesis

In a multichannel cochlear prosthesis, electrical interactions between electrodes impose severe limitations on dynamic range and selectivity. We present a theoretical model to cope with these limitations. Building a successful cochlear implant requires full custom-integrated circuits. We present the design of such a device, implemented in complementary metal oxide semiconductor technology. The area of the chip is 9 mm2 and it can stimulate 15 cochlear electrodes with current impulses.

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