scholarly journals A design method for active high-CMRR fully-differential circuits

2012 ◽  
Vol 1 (2) ◽  
pp. 103 ◽  
Author(s):  
Enrique Mario Spinelli ◽  
Gemma Hornero ◽  
Oscar Casas ◽  
Marcelo Haberman
Keyword(s):  
Design Method ◽  
Fully Differential ◽  
High Cmrr ◽  
Differential Circuits

scholarly journals A design method for active high-CMRR fully-differential circuits

2013 ◽  
Vol 1 (2) ◽  
pp. 103
Author(s):  
Enrique Mario Spinelli ◽  
Gemma Hornero ◽  
Oscar Casas ◽  
Marcelo Haberman
Keyword(s):  
Design Method ◽  
Fully Differential ◽  
High Cmrr ◽  
Differential Circuits

Noise Analysis of Fully Differential Circuits

2012 ◽  
Vol 10 (4) ◽  
pp. 1889-1892 ◽  
Author(s):  
Enrique Spinelli ◽  
Marcelo Haberman
Keyword(s):  
Noise Analysis ◽  
Fully Differential ◽  
Differential Circuits

scholarly journals An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Wilmar Carvajal ◽  
Wilhelmus Van Noije
Keyword(s):  
Analog Circuits ◽  
Bottom Plate ◽  
Pipeline Adc ◽  
Digital Correction ◽  
Fully Differential ◽  
Reconfigurable Design ◽  
Parallel Pipeline ◽  
Block Level ◽  
Differential Circuits ◽  
Time Interleaved

This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayout results are shown.

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