Semi-circular angle-based one bit circle generation algorithm on a hexagonal grid

2016 ◽  
Vol 8 (3) ◽  
pp. 199
Author(s):  
Manoharan Prabukumar ◽  
Bimal Kumar Ray
Keyword(s):  
Hexagonal Grid ◽  
Generation Algorithm

scholarly journals Duality and Dimensionality Reduction Discrete Line Generation Algorithm for a Triangular Grid

2018 ◽  
Vol 7 (10) ◽  
pp. 391 ◽  
Author(s):  
Lingyu Du ◽  
Qiuhe Ma ◽  
Jin Ben ◽  
Rui Wang ◽  
Jiahao Li
Keyword(s):  
Dimensionality Reduction ◽  
Path Model ◽  
Triangular Grid ◽  
Weak Duality ◽  
Vector Data ◽  
Hexagonal Grid ◽  
Generation Algorithm ◽  
Discrete Line ◽  
Hexagonal Grids ◽  
Line Generation

Vectors are a key type of geospatial data, and their discretization, which involves solving the problem of generating a discrete line, is particularly important. In this study, we propose a method for constructing a discrete line mathematical model for a triangular grid based on a “weak duality” hexagonal grid, to overcome the drawbacks of existing discrete line generation algorithms for a triangular grid. First, a weak duality relationship between triangular and hexagonal grids is explored. Second, an equivalent triangular grid model is established based on the hexagonal grid, using this weak duality relationship. Third, the two-dimensional discrete line model is solved by transforming it into a one-dimensional optimal wandering path model. Finally, we design and implement the dimensionality reduction generation algorithm for a discrete line in a triangular grid. The results of our comparative experiment indicate that the proposed algorithm has a computation speed that is approximately 10 times that of similar existing algorithms; in addition, it has better fitting effectiveness. Our proposed algorithm has broad applications, and it can be used for real-time grid transformation of vector data, discrete global grid system (DGGS), and other similar applications.

Reduction of Pixel Occurrences in Background Updating

2012 ◽  
Vol 17 (4) ◽  
pp. 45-50
Author(s):  
Zbigniew Bubliński ◽  
Piotr Pawlik
Keyword(s):  
Moving Objects ◽  
Time Rate ◽  
Generation Algorithm ◽  
Modified Method ◽  
Background Updating

Abstract The paper presents the modification of background generation algorithm based on analysis of the frequency of occurrences of pixels. The proposed solution allows the generation of the background and its updating, the introduced parameter allows to adjust the algorithm according to the time rate of changes in the image. The results show that the modified method can be applied in many tasks related to the detection and analysis of moving objects.

BCL::Conf – Improved Open-Source Knowledge-Based Conformation Sampling using the Crystallographic Open Database

2020 ◽  
Author(s):  
Jeffrey Mendenhall ◽  
Benjamin Brown ◽  
Sandeepkumar Kothiwale ◽  
Jens Meiler
Keyword(s):  
Ligand Binding ◽  
Open Source ◽  
Operating Systems ◽  
Generation Algorithm ◽  
Rotamer Library ◽  
Conformer Generation ◽  
Knowledge Based

<div>This paper describes recent improvements made to the BCL::Conf rotamer generation algorithm and comparison of its performance against other freely available and commercial conformer generation software. We demonstrate that BCL::Conf, with the use of rotamers derived from the COD, more effectively recovers crystallographic ligand-binding conformations seen in the PDB than other commercial and freely available software. BCL::Conf is now distributed with the COD-derived rotamer library, free for academic use. The BCL can be downloaded at <a href="http://meilerlab.org/index.php/bclcommons/show/b_apps_id/1">http://meilerlab.org/ bclcommons</a> for Windows, Linux, or Apple operating systems.<br></div>

A Quantification Method for Fitting Directed Arcs to Hexagonal Grid Edges

2018 ◽  
Vol 30 (4) ◽  
pp. 557
Author(s):  
Han Zhang ◽  
Jing Li ◽  
Pin Lyu ◽  
Yongzhi Xu ◽  
Gelin Liu
Keyword(s):  
Hexagonal Grid ◽  
Quantification Method

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Sign in / Sign up

Export Citation Format

Share Document