High-performance scheduling algorithms for buffered crossbar switches

2002 ◽  
Author(s):  
Lotfi Mhamdi
Keyword(s):  
High Performance ◽  
Scheduling Algorithms ◽  
Crossbar Switches ◽  
Buffered Crossbar Switches

Hipernetch: High-Performance FPGA Network Switch

2022 ◽  
Vol 15 (1) ◽  
pp. 1-31
Author(s):  
Philippos Papaphilippou ◽  
Jiuxi Meng ◽  
Nadeen Gebara ◽  
Wayne Luk
Keyword(s):  
High Frequency ◽  
High Performance ◽  
Data Centers ◽  
Round Robin ◽  
Switching Performance ◽  
Wide Range ◽  
Crossbar Switches ◽  
High Bandwidth ◽  
Network Switch ◽  
Network Switches

We present Hipernetch, a novel FPGA-based design for performing high-bandwidth network switching. FPGAs have recently become more popular in data centers due to their promising capabilities for a wide range of applications. With the recent surge in transceiver bandwidth, they could further benefit the implementation and refinement of network switches used in data centers. Hipernetch replaces the crossbar with a “combined parallel round-robin arbiter”. Unlike a crossbar, the combined parallel round-robin arbiter is easy to pipeline, and does not require centralised iterative scheduling algorithms that try to fit too many steps in a single or a few FPGA cycles. The result is a network switch implementation on FPGAs operating at a high frequency and with a low port-to-port latency. Our proposed Hipernetch architecture additionally provides a competitive switching performance approaching output-queued crossbar switches. Our implemented Hipernetch designs exhibit a throughput that exceeds 100 Gbps per port for switches of up to 16 ports, reaching an aggregate throughput of around 1.7 Tbps.

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