scholarly journals Clock Math — a System for Solving SLEs Exactly

10.14311/1795 ◽  
2013 ◽  
Vol 53 (2) ◽  
Author(s):  
Jakub Hladík ◽  
Róbert Lórencz ◽  
Ivan Šimeček
Keyword(s):  
Hybrid System ◽  
Chinese Remainder Theorem ◽  
Linear Equations ◽  
Floating Point ◽  
Rounding Errors ◽  
Systems Of Linear Equations ◽  
Floating Point Numbers

In this paper, we present a GPU-accelerated hybrid system that solves ill-conditioned systems of linear equations exactly. Exactly means without rounding errors due to using integer arithmetics. First, we scale floating-point numbers up to integers, then we solve dozens of SLEs within different modular arithmetics and then we assemble sub-solutions back using the Chinese remainder theorem. This approach effectively bypasses current CPU floating-point limitations. The system is capable of solving Hilbert’s matrix without losing a single bit of precision, and with a significant speedup compared to existing CPU solvers.

GENETIC ALGORITHMS, FLOATING POINT NUMBERS AND APPLICATIONS

2005 ◽  
Vol 16 (11) ◽  
pp. 1811-1816 ◽  
Author(s):  
YORICK HARDY ◽  
WILLI-HANS STEEB ◽  
RUEDI STOOP
Keyword(s):  
Genetic Algorithm ◽  
Genetic Algorithms ◽  
Linear Equations ◽  
Floating Point ◽  
The Core ◽  
Point Number ◽  
Floating Point Number ◽  
Roots Of Polynomials ◽  
Bitwise Operations ◽  
Floating Point Numbers

The core in most genetic algorithms is the bitwise manipulations of bit strings. We show that one can directly manipulate the bits in floating point numbers. This means the main bitwise operations in genetic algorithm mutations and crossings are directly done inside the floating point number. Thus the interval under consideration does not need to be known in advance. For applications, we consider the roots of polynomials and finding solutions of linear equations.

New Research Results of Algorithms for Analysis of Changing Electric Circuits

2020 ◽  
Vol 63 (6) ◽  
pp. 29-36
Author(s):  
Ivan Lebedev ◽  
◽  
Nikolai Savelov ◽  
Keyword(s):  
Numerical Experiments ◽  
Linear Equations ◽  
Iterative Refinement ◽  
Floating Point ◽  
Electrical Circuits ◽  
Electric Circuits ◽  
Research Results ◽  
Systems Of Linear Equations ◽  
New Research ◽  
Refinement Algorithm

New research results in the field of accelerated analysis of linear and linearizable electrical circuits with variable elements are presented. The considered algorithms are based on a new modification of Gaussian elim-ination for solution of systems of linear equations. The researches was directed on a systematic thorough study of the phenomenon of quasi-stabilization of the error discovered by the authors during multiple repeated cir-cuit analyzes. The Sherman-Morrison algorithm and the iterative refinement algorithm are considered as alter-natives. To control the results of numerical experiments, the representation of floating-point numbers in the bi-nary128 format of the IEEE 754 standard is used. A method for the machine formation of mathematical models of circuits with an unlimited number of elements is proposed.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

On Some Properties of Semi-rings

2018 ◽  
pp. 35-50
Author(s):  
A. I. Belousov
Keyword(s):  
Linear Equations ◽  
Oriented Graph ◽  
Theoretical Computer Science ◽  
Alternative Methods ◽  
Main Role ◽  
Cost Matrix ◽  
Sequential Elimination ◽  
The Matrix ◽  
Systems Of Linear Equations ◽  
The Cost

The main objective of this paper is to prove a theorem according to which a method of successive elimination of unknowns in the solution of systems of linear equations in the semi-rings with iteration gives the really smallest solution of the system. The proof is based on the graph interpretation of the system and establishes a relationship between the method of sequential elimination of unknowns and the method for calculating a cost matrix of a labeled oriented graph using the method of sequential calculation of cost matrices following the paths of increasing ranks. Along with that, and in terms of preparing for the proof of the main theorem, we consider the following important properties of the closed semi-rings and semi-rings with iteration.We prove the properties of an infinite sum (a supremum of the sequence in natural ordering of an idempotent semi-ring). In particular, the proof of the continuity of the addition operation is much simpler than in the known issues, which is the basis for the well-known algorithm for solving a linear equation in a semi-ring with iteration.Next, we prove a theorem on the closeness of semi-rings with iteration with respect to solutions of the systems of linear equations. We also give a detailed proof of the theorem of the cost matrix of an oriented graph labeled above a semi-ring as an iteration of the matrix of arc labels.The concept of an automaton over a semi-ring is introduced, which, unlike the usual labeled oriented graph, has a distinguished "final" vertex with a zero out-degree.All of the foregoing provides a basis for the proof of the main theorem, in which the concept of an automaton over a semi-ring plays the main role.The article's results are scientifically and methodologically valuable. The proposed proof of the main theorem allows us to relate two alternative methods for calculating the cost matrix of a labeled oriented graph, and the proposed proofs of already known statements can be useful in presenting the elements of the theory of semi-rings that plays an important role in mathematical studies of students majoring in software technologies and theoretical computer science.

Printing floating-point numbers: a faster, always correct method

2016 ◽  
Vol 51 (1) ◽  
pp. 555-567
Author(s):  
Marc Andrysco ◽  
Ranjit Jhala ◽  
Sorin Lerner
Keyword(s):  
Floating Point ◽  
Correct Method ◽  
Floating Point Numbers
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