Clock Recovery with DGD-tolerant Phase Detector for CP-QPSK Receivers

2010 ◽  
Author(s):  
C. Hebebrand ◽  
A. Napoli ◽  
A. Bianciotto ◽  
S. Calabro ◽  
B. Spinnler ◽  
...  
Keyword(s):  
Clock Recovery ◽  
Phase Detector

A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data

2007 ◽  
Vol 54 (8) ◽  
pp. 1626-1635 ◽  
Author(s):  
Francesco Centurelli ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Clock Recovery ◽  
Phase Detector ◽  
Voltage Phase

Phase detector for data-clock recovery circuit

2002 ◽  
Vol 38 (4) ◽  
pp. 161 ◽  
Author(s):  
A. Hati ◽  
M. Ghosh ◽  
B.C. Sarkar
Keyword(s):  
Clock Recovery ◽  
Phase Detector

The Design and Simulation of a CMOS Digital PLL

2011 ◽  
Vol 48-49 ◽  
pp. 1227-1230
Author(s):  
Kai Yu Wang ◽  
Zhe Nan Tang ◽  
Tao Ge
Keyword(s):  
Communication Systems ◽  
Hard Core ◽  
Charge Pump ◽  
Digital Signal ◽  
Clock Recovery ◽  
Phase Detector ◽  
Center Frequency ◽  
Loop Filter ◽  
Parasitic Extraction ◽  
Locking Range

In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5μm CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz~60MHz, the locking time is less than 1.5μs, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.

scholarly journals An analysis of ADPLL applications in various fields

2020 ◽  
Vol 18 (2) ◽  
pp. 856
Author(s):  
R. Dinesh ◽  
Ramalatha Marimuthu
Keyword(s):  
Power Consumption ◽  
Clock Recovery ◽  
Phase Detector ◽  
Frequency Resolution ◽  
Frequency Range ◽  
Loop Filter ◽  
Digital Implementation ◽  
Clock Generation ◽  
Health Care Applications ◽  
Automatic Placement

<span>ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and digital PLL used for frequency synthesis, clock recovery circuit and synchronization give imprecise performance with respect to reliability, speed, power consumption, noise, locking speed, cost, etc. ADPLL overcomes the drawbacks of conventional PLL and digital PLL. In this paper, different approaches followed in All Digital Phase Locked Loop (ADPLL) for various applications are reviewed and their performance is compared based on components, modulation functions, frequency range, power utilization etc. In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator. The ADPLL outputs and the results are analyzed with micro wind tool. The design gives a frequency range from 1.0-5.5GHz with low power consumption and it can also be used for Clock generation applications. </span>

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