scholarly journals On-chip passive optical diode with low-power consumption

2018 ◽  
Vol 26 (25) ◽  
pp. 33463 ◽  
Author(s):  
Li Liu ◽  
Jin Yue ◽  
Xiaokang Fan ◽  
Wei Xue
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
On Chip ◽  
Optical Diode

On-chip optical diode with low power consumption

2017 ◽  
Author(s):  
Huaqing Qiu ◽  
Zhao Cheng ◽  
Feng Zhou ◽  
Jianji Dong ◽  
Xinliang Zhang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
On Chip ◽  
Optical Diode

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Reconfigurable on-chip communication link for efficient communication

2018 ◽  
Vol 7 (2-1) ◽  
pp. 417
Author(s):  
Beulah Hemalatha S ◽  
Vigneswaran T
Keyword(s):  
Genetic Algorithm ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Problems ◽  
Research Area ◽  
Low Power Consumption ◽  
Communication Link ◽  
Simulated System ◽  
Efficient Communication ◽  
On Chip

Application specific reconfiguration of On-chip communication link is a fast growing research area in system on chip (SoC) based system design. Optimization of the communication link is important to achieve a trade-off between efficient communication and low power consumption. So achieving both efficient communication and low power consumption requires a special optimization mechanism. Such Optimization problems can be solved using a genetic algorithm. Here, in this paper genetic algorithm based On-chip communication link reconfiguration is presented. The algorithm will optimize efficiency of communication link with constrain of low power consumption. The parameters involved in power consumption and efficient communication link are coded in the chromosomes. By evolutionary iteration the optimal parameters of the communication link are derived that is used for the communication link successfully in the simulated system. The performance of the simulated system is analyzed which shows the out performance of the proposed system.

scholarly journals Design of Completion Detectors in Asynchronous Communication System

2020 ◽  
Vol 9 (3) ◽  
pp. 3329-3334
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Communication System ◽  
Implementation Process ◽  
Asynchronous Communication ◽  
Digital Design ◽  
Low Power Consumption ◽  
Asynchronous Design ◽  
Global Clock ◽  
On Chip

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.

scholarly journals A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 84066-84081 ◽  
Author(s):  
Aravindhan Alagarsamy ◽  
Lakshminarayanan Gopalakrishnan ◽  
Sundarakannan Mahilmaran ◽  
Seok-Bum Ko
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Mapping Approach ◽  
On Chip ◽  
Self Adaptive

Evaluation of low power consumption network on chip routing architecture

2021 ◽  
Vol 82 ◽  
pp. 103809
Author(s):  
Arulananth T S ◽  
Baskar M ◽  
Udhaya Sankar S M ◽  
R. Thiagarajan ◽  
Arul Dalton G ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network On Chip ◽  
Low Power Consumption ◽  
On Chip

scholarly journals Design and Implementation of an On-Chip Low-Power and High-Flexibility System for Data Acquisition and Processing of an Inertial Measurement Unit

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 462 ◽  
Author(s):  
Zhenyi Gao ◽  
Bin Zhou ◽  
Yang Li ◽  
Lei Yang ◽  
Xiang Li ◽  
...  
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Low Power ◽  
Inertial Measurement Unit ◽  
Measurement Unit ◽  
Low Power Consumption ◽  
Inertial Measurement ◽  
Static Power ◽  
On Chip ◽  
Application Specific

For signal processing of a Micro-Electro-Mechanical System (MEMS) Inertial Measurement Unit (IMU), a digital-analog hybrid system-on-chip (SoC) with small area and low power consumption was designed and implemented in this paper. To increase the flexibility of the processing circuit, the designed SoC integrates a low-power processor and supports three startup or debugging modes for different application scenarios. An application-specific computing module and communication interface are designed in the circuit to meet the requirements of IMU signal processing. The configurable clock allows users to dynamically balance computing speed and power consumption in their applications. The chip was taped out under SMIC 180 nm CMOS technology and tested for performance. The results show that the chip’s maximum running frequency is 105 MHz. The total area is 33.94 mm 2 . The dynamic and static power consumption are 0.65 mW/MHz and 0.30 mW/MHz, respectively. When the system clock is 25 MHz, the dynamic and static power consumption of the chip is 76 mW and 66 mW, and the dynamic and static power consumption of the FPGA level are 634 mW and 520 mW. The results verify the superiority of the application specific integrated circuit (ASIC) solution in terms of integration and low power consumption.

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