scholarly journals Characterization of a fully integrated heterogeneous silicon/III-V colliding pulse mode-locked laser with on-chip feedback

2018 ◽  
Vol 26 (8) ◽  
pp. 9714 ◽  
Author(s):  
Songtao Liu ◽  
Tin Komljenovic ◽  
Sudharsanan Srinivasan ◽  
Erik Norberg ◽  
Gregory Fish ◽  
...  
Keyword(s):  
Pulse Mode ◽  
Fully Integrated ◽  
Mode Locked Laser ◽  
On Chip

A Heterogeneously Integrated III-V/Si Colliding Pulse Mode-locked Laser with On-chip Feedback

2018 ◽  
Author(s):  
Songtao Liu ◽  
Tin Komljenovic ◽  
Sudharsanan Srinivasan ◽  
Erik Norberg ◽  
Gregory Fish ◽  
...  
Keyword(s):  
Pulse Mode ◽  
Mode Locked Laser ◽  
On Chip

1  GHz InP on-chip monolithic extended cavity colliding-pulse mode-locked laser

2017 ◽  
Vol 42 (12) ◽  
pp. 2318 ◽  
Author(s):  
R. Guzmán ◽  
C. Gordon ◽  
L. Orbe ◽  
G. Carpintero
Keyword(s):  
Pulse Mode ◽  
Extended Cavity ◽  
Mode Locked Laser ◽  
On Chip

scholarly journals On-Chip Colliding Pulse Mode-locked laser diode (OCCP-MLLD) using multimode interference reflectors

2015 ◽  
Vol 23 (11) ◽  
pp. 14666 ◽  
Author(s):  
Carlos Gordón ◽  
Robinson Guzmán ◽  
Vinicio Corral ◽  
Xaveer Leijtens ◽  
Guillermo Carpintero
Keyword(s):  
Laser Diode ◽  
Pulse Mode ◽  
Multimode Interference ◽  
Mode Locked Laser ◽  
On Chip

CMOS fully-integrated wireless temperature sensors with on-chip antenna

2009 ◽  
Author(s):  
Fabio Aquilino ◽  
Francesco G. Della Corte ◽  
Letizia Fragomeni ◽  
Massimo Merenda ◽  
Fabio Zito
Keyword(s):  
Temperature Sensors ◽  
Fully Integrated ◽  
On Chip Antenna ◽  
On Chip

scholarly journals Noise and Breakdown Characterization of SPAD Detectors with Time-Gated Photon-Counting Operation

Sensors ◽  
2021 ◽  
Vol 21 (16) ◽  
pp. 5287
Author(s):  
Hiwa Mahmoudi ◽  
Michael Hofbauer ◽  
Bernhard Goll ◽  
Horst Zimmermann
Keyword(s):  
Breakdown Voltage ◽  
Single Photon ◽  
Photon Counting ◽  
Low Noise ◽  
Dark Count ◽  
Fully Integrated ◽  
Trade Offs ◽  
And Performance ◽  
Noise Models

Being ready-to-detect over a certain portion of time makes the time-gated single-photon avalanche diode (SPAD) an attractive candidate for low-noise photon-counting applications. A careful SPAD noise and performance characterization, however, is critical to avoid time-consuming experimental optimization and redesign iterations for such applications. Here, we present an extensive empirical study of the breakdown voltage, as well as the dark-count and afterpulsing noise mechanisms for a fully integrated time-gated SPAD detector in 0.35-μm CMOS based on experimental data acquired in a dark condition. An “effective” SPAD breakdown voltage is introduced to enable efficient characterization and modeling of the dark-count and afterpulsing probabilities with respect to the excess bias voltage and the gating duration time. The presented breakdown and noise models will allow for accurate modeling and optimization of SPAD-based detector designs, where the SPAD noise can impose severe trade-offs with speed and sensitivity as is shown via an example.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

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