Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory

2018 ◽  
Vol 11 (20) ◽  
pp. 983-993
Author(s):  
Tomohiro Yokota ◽  
Shigeyoshi Watanabe
Keyword(s):  
Parallel Processing ◽  
Flash Memory ◽  
Logic Circuit ◽  
Nand Flash ◽  
Reconfigurable Logic ◽  
Nand Flash Memory ◽  
Process Technology

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

Integrating Novel Packaging Technologies for Large Scale Computer Systems

2009 ◽  
Author(s):  
James Mitchell ◽  
John Cunningham ◽  
Ashok V. Krishnamoorthy ◽  
Robert Drost ◽  
Ron Ho
Keyword(s):  
Flash Memory ◽  
Large Scale ◽  
Cmos Technology ◽  
Capacitive Coupling ◽  
System Level ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Large Piece ◽  
Face To Face

Proximity Communication (PxC) enables VLSI chips placed face-to-face to communicate using close-field capacitive coupling. In a 90 nm standard CMOS technology, using the packaging techniques described in this paper, PxC provides chip-to-chip latency of 2.5 ns at 4 Gb/s per channel with less than 2.5 mW/Gb/s, an areal bandwidth density of 0.83 Tb/s/mm2, and a BER less than 10−15. At a system level, the benefits of PxC scale directly with the number of chips that can be packaged together, because PxC enables designers to aggregate multiple chips that perform as a single large piece of silicon. The chips can also be heterogeneous to provide an optimized mix of process technology and functionality, such as integrating DRAM chips, NAND flash memory, and CMOS processor chips. In this paper we describe packaging advances and technology prototypes that enable PxC and provide its system-level benefits.

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array
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