Circuit Simulation of the Modified Lorenz System

2013 ◽  
Vol 10 (15) ◽  
pp. 4763-4772 ◽  
Author(s):  
Guoqing Huang
Keyword(s):  
Lorenz System ◽  
Circuit Simulation

A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability

2021 ◽  
Vol 26 (6) ◽  
pp. 1-24
Author(s):  
Saranyu Chattopadhyay ◽  
Pranesh Santikellur ◽  
Rajat Subhra Chakraborty ◽  
Jimson Mathew ◽  
Marco Ottavi
Keyword(s):  
Lorenz System ◽  
High Reliability ◽  
Circuit Simulation ◽  
Design Framework ◽  
Chaotic Circuit ◽  
Hybrid Cmos ◽  
Function Design ◽  
Hardware Realization ◽  
Arbiter Puf ◽  
Detailed Circuit

Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

Nonlinear Circuit Simulation and Modeling

2018 ◽  
Author(s):  
José Carlos Pedro ◽  
David E. Root ◽  
Jianjun Xu ◽  
Luís Cótimos Nunes
Keyword(s):  
Circuit Simulation ◽  
Simulation And Modeling ◽  
Nonlinear Circuit

Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe

2013 ◽  
Author(s):  
Jong Hak Lee ◽  
Jong Eun Kim ◽  
Chang Su Park ◽  
Nam Il Kim ◽  
Jang Won Moon ◽  
...  
Keyword(s):  
Leakage Current ◽  
Circuit Simulation ◽  
The State ◽  
Physical Analysis ◽  
Cross Sectional ◽  
Hard Mask ◽  
Current Flows ◽  
Voltage Contrast ◽  
The One ◽  
Zero Voltage

Abstract In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.

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