Gate Sizing | ScienceGate

Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment

10.1561/9781601985439 ◽

2012 ◽

Cited By ~ 1

Author(s):

John Lee ◽

Puneet Gupta

Keyword(s):

Threshold Voltage ◽

Gate Sizing ◽

Circuit Optimization

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Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm

Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09 ◽

10.1145/1629911.1630042 ◽

2009 ◽

Cited By ~ 14

Author(s):

Weiguang Sheng ◽

Liyi Xiao ◽

Zhigang Mao

Keyword(s):

Genetic Algorithm ◽

Soft Error ◽

Gate Sizing ◽

Standard Cell ◽

Multi Objective ◽

Multi Objective Genetic Algorithm ◽

Error Optimization

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Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. ◽

10.1109/iccad.2004.1382535 ◽

2005 ◽

Cited By ~ 12

Author(s):

D. Sinha ◽

Hai Zhou

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Timing Constraints ◽

Crosstalk Reduction

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Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.101 ◽

2006 ◽

Cited By ~ 3

Author(s):

N. Hanchate ◽

N. Ranganathan

Keyword(s):

Gate Sizing ◽

Crosstalk Noise ◽

Interconnect Delay ◽

Noise Optimization

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Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) ◽

10.1109/iolts.2018.8474275 ◽

2018 ◽

Author(s):

Xuebing Cao ◽

Liyi Xiao ◽

Linzhe Li ◽

Jie Li ◽

Jiaqiang Li ◽

...

Keyword(s):

Particle Swarm Optimization ◽

Optimization Algorithm ◽

Particle Swarm Optimization Algorithm ◽

Particle Swarm ◽

Soft Error ◽

Gate Sizing ◽

Combinational Circuit ◽

Swarm Optimization ◽

Multi Objective ◽

Error Optimization

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Optimal gate sizing for coupling-noise reduction

Proceedings of the 2004 international symposium on Physical design - ISPD '04 ◽

10.1145/981066.981104 ◽

2004 ◽

Cited By ~ 4

Author(s):

Debjit Sinha ◽

Hai Zhou ◽

Chris C. N. Chu

Keyword(s):

Noise Reduction ◽

Gate Sizing ◽

Coupling Noise

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Postroute Gate Sizing for Crosstalk Noise Reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2004.836736 ◽

2004 ◽

Vol 23 (12) ◽

pp. 1670-1677 ◽

Cited By ~ 12

Author(s):

M.R. Becer ◽

D. Blaauw ◽

I. Algor ◽

R. Panda ◽

C. Oh ◽

...

Keyword(s):

Noise Reduction ◽

Gate Sizing ◽

Crosstalk Noise

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Sensitivity-guided metaheuristics for accurate discrete gate sizing

Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 ◽

10.1145/2429384.2429428 ◽

2012 ◽

Cited By ~ 31

Author(s):

Jin Hu ◽

Andrew B. Kahng ◽

SeokHyeong Kang ◽

Myung-Chul Kim ◽

Igor L. Markov

Keyword(s):

Gate Sizing ◽

Discrete Gate Sizing

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Gate sizing using Geometric Programming

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS) ◽

10.1109/lascas.2011.5750263 ◽

2011 ◽

Cited By ~ 1

Author(s):

Gracieli Posser ◽

Guilherme Flach ◽

Gustavo Wilke ◽

Ricardo Reis

Keyword(s):

Geometric Programming ◽

Gate Sizing

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A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2009.2035575 ◽

2010 ◽

Vol 29 (2) ◽

pp. 223-234 ◽

Cited By ~ 39

Author(s):

Yifang Liu ◽

Jiang Hu

Keyword(s):

Threshold Voltage ◽

Gate Sizing

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