ESD Design and Optimization in Advanced CMOS SOI Technology

2018 ◽  
pp. 284-309
Author(s):  
You Li
Author(s):  
Taddese Mekonnen Ambay ◽  
Philipp Schick ◽  
Michael Grimm ◽  
Maximilian Sager ◽  
Felix Schneider ◽  
...  

2018 ◽  
Vol 13 (2) ◽  
pp. 107
Author(s):  
Flur Ismagilov ◽  
Vajcheslav Vavilov ◽  
Oksana Yushkova ◽  
Vladimir Bekuzin ◽  
Alexey Veselov

Author(s):  
V.F. Kravchenko ◽  
◽  
Yiyang Luo ◽  
V.I. Lutsenko ◽  
◽  
...  

2020 ◽  
Vol 63 (11) ◽  
pp. 586-595
Author(s):  
Alexander Korotkov ◽  
Dmitry Morozov ◽  
Mikhail Pilipko ◽  
Mikhail Yenuchenko

Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.


Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.


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