PEGASUS: A System for Large-Scale Graph Processing

2014 ◽  
pp. 270-301 ◽  
Keyword(s):  
Large Scale ◽  
Graph Processing

Correction To: Large scale graph processing systems: survey and an experimental evaluation

2018 ◽  
Vol 21 (2) ◽  
pp. 1455-1455 ◽  
Author(s):  
Omar Batarfi ◽  
Radwa El Shawi ◽  
Ayman G. Fayoumi ◽  
Reza Nouri ◽  
Seyed-Mehdi-Reza Beheshti ◽  
...  
Keyword(s):  
Experimental Evaluation ◽  
Large Scale ◽  
Graph Processing

FDGLib: A Communication Library for Efficient Large-Scale Graph Processing in FPGA-Accelerated Data Centers

2021 ◽  
Vol 36 (5) ◽  
pp. 1051-1070
Author(s):  
Yu-Wei Wu ◽  
Qing-Gang Wang ◽  
Long Zheng ◽  
Xiao-Fei Liao ◽  
Hai Jin ◽  
...  
Keyword(s):  
Large Scale ◽  
Data Centers ◽  
Graph Processing

Replication-Based Fault-Tolerance for Large-Scale Graph Processing

2018 ◽  
Vol 29 (7) ◽  
pp. 1621-1635 ◽  
Author(s):  
Rong Chen ◽  
Youyang Yao ◽  
Peng Wang ◽  
Kaiyuan Zhang ◽  
Zhaoguo Wang ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Large Scale ◽  
Graph Processing

scholarly journals Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips

2022 ◽  
Vol 27 (1) ◽  
pp. 1-30
Author(s):  
Mengke Ge ◽  
Xiaobing Ni ◽  
Xu Qi ◽  
Song Chen ◽  
Jinglei Huang ◽  
...  
Keyword(s):  
Large Scale ◽  
Small World ◽  
Brain Network ◽  
Graph Processing ◽  
Hop Count ◽  
Scale Free ◽  
Large Scale Network ◽  
Average Latency ◽  
Scale Network ◽  
The Brain

Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this article, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. First, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications, considering the modularity of the brain-network-inspired topologies, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator BookSim2 is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the brain-network-inspired network-on-chips (NoCs) generated by the proposed method present significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.

scholarly journals Large-Scale Graph Processing Analysis using Supercomputer Cluster

2017 ◽  
Vol 801 ◽  
pp. 012079
Author(s):  
Alfrido Vildario ◽  
Fitriyani ◽  
Galih Nugraha Nurkahfi
Keyword(s):  
Large Scale ◽  
Graph Processing
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