Advanced Effects of Scaled MOS Transistors

2014 ◽  
pp. 253-303
Keyword(s):  
Mos Transistors

ANALYSIS OF HOT CARRIER DEGRADATION IN AC STRESSED N-CHANNEL MOS TRANSISTORS USING THE CHARGE PUMPING TECHNIQUE

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-651-C4-655 ◽  
Author(s):  
R. BELLENS ◽  
P. HEREMANS ◽  
G. GROESENEKEN ◽  
H. E. MAES
Keyword(s):  
Mos Transistors ◽  
Charge Pumping ◽  
Hot Carrier ◽  
Hot Carrier Degradation

A High PSRR Bandgap Voltage Reference with Virtually Diode-Connected MOS Transistors

2010 ◽  
Vol E93-C (12) ◽  
pp. 1708-1712 ◽  
Author(s):  
Kianoush SOURI ◽  
Hossein SHAMSI ◽  
Mehrshad KAZEMI ◽  
Kamran SOURI
Keyword(s):  
Voltage Reference ◽  
Mos Transistors ◽  
Bandgap Voltage Reference

ОСОБЕННОСТИ ЭКСТРАКЦИИ SPICE-МОДЕЛЕЙ ТРАНЗИСТОРОВ ДЛЯ ТЕХНОЛОГИЙ КНИ ГЛУБОКОГО СУБМИКРОННОГО УРОВНЯ

2020 ◽  
Vol 96 (3s) ◽  
pp. 680-683
Author(s):  
А.В. Нуштаев ◽  
А.Г. Потупчик
Keyword(s):  
Process Design ◽  
Development Process ◽  
Dynamic Parameters ◽  
Mos Transistors ◽  
Spice Model

Разработаны тестовые структуры для экстракции и верификации статических и динамических параметров SPICE-моделей транзисторов. Проведена экстракция SPICE-моделей МОП-транзисторов А-типа в рамках разработки комплекта средств проектирования для технологии КНИ-180. Проведена верификация статических и динамических параметров полученных моделей транзисторов. The paper highlights test structures for the extraction and verification of static and dynamic parameters of the transistor SPICE model. The SPICE models of A-type MOS transistors for development process design kit for S0I180 technology have been extracted. Verification of static and dynamic parameters of the obtained transistor models has been carried out.

ВЛИЯНИЕ ТВЕРДОФАЗНОЙ РЕКРИСТАЛЛИЗАЦИИ С ДВОЙНОЙ ИМПЛАНТАЦИЕЙ НА ПЛОТНОСТЬ СТРУКТУРНЫХ ДЕФЕКТОВ В УЛЬТРАТОНКИХ СЛОЯХ КРЕМНИЯ НА САПФИРЕ

2020 ◽  
Vol 96 (3s) ◽  
pp. 154-159
Author(s):  
Н.Н. Егоров ◽  
С.А. Голубков ◽  
С.Д. Федотов ◽  
В.Н. Стаценко ◽  
А.А. Романов ◽  
...  
Keyword(s):  
Dislocation Density ◽  
Solid Phase ◽  
Modern Method ◽  
Structural Defects ◽  
Structural Quality ◽  
Mos Transistors ◽  
Ultrathin Layers ◽  
Heteroepitaxial Layers ◽  
Xrd And Tem

Высокая плотность структурных дефектов является основной проблемой при изготовлении электроники на гетероструктурах «кремний на сапфире» (КНС). Современный метод получения ультратонких структур КНС с помощью твердофазной эпитаксиальной рекристаллизации позволяет значительно снизить дефектность в гетероэпитаксиальном слое КНС. В данной работе ультратонкие (100 нм) слои КНС были получены путем рекристаллизации и утонения субмикронных (300 нм) слоев кремния на сапфире, обладающих различным структурным качеством. Плотность структурных дефектов в слоях КНС оценивалась с помощью рентгеноструктурного анализа и просвечивающей электронной микроскопии. Кривые качания от дифракционного отражения Si(400), полученные в ω-геометрии, продемонстрировали максимальную ширину на полувысоте пика не более 0,19-0,20° для ультратонких слоев КНС толщиной 100 нм. Формирование структурно совершенного субмикронного слоя КНС 300 нм на этапе газофазной эпитаксии обеспечивает существенное уменьшение плотности дислокаций в ультратонком кремнии на сапфире до значений ~1 • 104 см-1. Тестовые n-канальные МОП-транзисторы на ультратонких структурах КНС характеризовались подвижностью носителей в канале 725 см2 Вс-1. The high density of structural defects is the main problem on the way to the production of electronics on silicon-on-sapphire (SOS) heteroepitaxial wafers. The modern method of obtaining ultrathin SOS wafers is solid-phase epitaxial recrystallization which can significantly reduce the density of defects in the SOS heteroepitaxial layers. In the current work, ultrathin (100 nm) SOS layers were obtained by recrystallization and thinning of submicron (300 nm) SOS layers, which have various structural quality. The density of structural defects in the layers was estimated by using XRD and TEM. Full width at half maximum of rocking curves (ω-geometry) was no more than 0.19-0.20° for 100 nm ultra-thin SOS layers. The structural quality of 300 nm submicron SOS layers, which were obtained by CVD, depends on dislocation density in 100 nm ultrathin layers. The dislocation density in ultrathin SOS layers was reduced by ~1 • 104 cm-1 due to the utilization of the submicron SOS with good crystal quality. Test n-channel MOS transistors based on ultra-thin SOS wafers were characterized by electron mobility in the channel 725 cm2 V-1 s-1.

scholarly journals A Study on the Variable Inductor Design by Switching the Main Paths and the Coupling Coils

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1856
Author(s):  
Yen-Chung Chiang ◽  
Juo-Chen Chen ◽  
Yu-Hsin Chang
Keyword(s):  
Design Method ◽  
The Other ◽  
Cmos Process ◽  
Mos Transistors ◽  
Quality Factors ◽  
Process Technology ◽  
Variation Versus ◽  
Variable Inductor ◽  
Metal Layers ◽  
Coupled Coils

In a radio frequency (RF) system, it is possible to use variable inductors for providing tunable or selective frequency range. Variable inductors can be implemented by the microelectromechanical system (MEMS) process or by using transistors as switches to change the routing of coils or coupling quantities. In this paper, we investigated the design method of a variable inductor by using MOS transistors to switch the main coil paths and the secondary coupled coils. We observed the effects of different metal layers, turn numbers, and layout arrangements for secondary-coupled coils and compared their characteristics on the inductances and quality factors. We implemented two chips in the 0.18 m CMOS process technology for each kind of arrangement for verification. One inductor can achieve inductance values from about 300 pH to 550 pH, and the other is between 300 pH and 575 pH, corresponding to 59.3% and 62.5%, respectively, inductance variation range at 4 GHz frequency. Additionally, their fine step sizes of the switched inductances are from 0.5% to 6% for one design, and 1% to 12.5% for the other. We found that both designs achieved a large inductance tuning range and moderate inductance step sizes with a slight difference behavior on the inductance variation versus frequency.

scholarly journals Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4092
Author(s):  
Grzegorz Blakiewicz ◽  
Jacek Jakusz ◽  
Waldemar Jendernalik
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Boost Converter ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Thermoelectric Energy ◽  
On Chip ◽  
Voltage Swing ◽  
High Output Voltage ◽  
High Output

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

Complementary MOS transistors

1966 ◽  
Vol 9 (10) ◽  
pp. 991-1008 ◽  
Author(s):  
M.H. White ◽  
J.R. Cricchi
Keyword(s):  
Mos Transistors

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

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