Embedded Systems Code Optimization and Power Consumption

2017 ◽  
pp. 97-116
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Code Optimization

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Code Optimization for Embedded Systems

2003 ◽  
Author(s):  
Keith D. Cooper ◽  
Devika Subramanian ◽  
Linda Torczon
Keyword(s):  
Embedded Systems ◽  
Code Optimization

scholarly journals Microprocessors KOMDIV for High Performance Embedded Systems

2021 ◽  
Vol 7 (3) ◽  
Author(s):  
S.G. Bobkov
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
High Performance ◽  
Clock Cycle ◽  
Embedded Computing ◽  
Computing Systems ◽  
Processor Performance

The problems of creating of high-performance embedded computing systems based on microprocessors KOMDIV is considered. Processor performance is dependent upon three characteristics: clock cycle, clock cycles per instruction, and instruction count. These characteristics for microprocessors KOMDIV are optimized using parameter performance/power consumption and requirements of embedded systems.

Performance and power consumption evaluation of concurrent queue implementations in embedded systems

2014 ◽  
Vol 30 (2) ◽  
pp. 165-175 ◽  
Author(s):  
Lazaros Papadopoulos ◽  
Ivan Walulya ◽  
Paul Renaud-Goud ◽  
Philippas Tsigas ◽  
Dimitrios Soudris ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Power Consumption

scholarly journals Hardware-Enhanced Protection for the Runtime Data Security in Embedded Systems

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 52 ◽  
Author(s):  
Weike Wang ◽  
Xiaobing Zhang ◽  
Qiang Hao ◽  
Zhun Zhang ◽  
Bin Xu ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Data Security ◽  
Memory Access ◽  
Low Power Consumption ◽  
Replay Attack ◽  
Protection Method ◽  
Xor Operation ◽  
Hardware Overhead ◽  
Integrity Protection

At present, the embedded systems are facing various kinds of attacks, especially for the data stored in the external memories. This paper presents a hardware-enhanced protection method to protect the data integrity and confidentiality at runtime, preventing the data from spoofing attack, splicing attack, replay attack, and some malicious analysis. For the integrity protection, the signature is calculated by the hardware implemented Lhash engine before the data sending off the chip, and the signature of the data block is recalculated and compared with the decrypted one at the load time. For the confidentiality protection, an AES encryption engine is used to generate the key stream, the plain data and the cipher data can translate through a simple XOR operation. The hardware cryptographic engines are optimized to work simultaneously with the memory access operation, which reduces the hardware overhead and the performance overhead. We implement the proposed architecture within OR1200 processor on Xilinx Virtex 5 FPGA platform. The experiment results show that the proposed hardware-enhanced protection method can preserve the integrity and confidentiality of the runtime data in the embedded systems with low power consumption and a marginal area footprint. The performance overhead is less than 2.27% according to the selected benchmarks.

scholarly journals Performance and energy optimization of heterogeneous CPU-GPU systems for embedded applications

2021 ◽  
Author(s):  
Abdullah Siddiqui
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Optimization Algorithm ◽  
Heterogeneous Computing ◽  
Energy Optimization ◽  
Systems Design ◽  
Application Partitioning ◽  
Computing Platforms ◽  
Embedded Applications ◽  
Software Partitioning

One of the most critical steps of embedded systems design is Hardware-Software partitioning. It is characterized by distributing the components of an application between hardware and software such that the user defined system constraints are satisfied. Heterogeneous computing platforms consisting of CPUs and GPUs have tremendous potential for enhancing the performance of embedded applications. The challenge of application partitioning for CPU-GPU mapping is much greater on such platforms due to their unique and diverse characteristics. In this thesis, an optimization algorithm is devised and presented for partitioning and mapping computational tasks on CPU-GPU platforms while keeping a check on the power consumption. Our methodology also uses parallelism in applications and their tasks by utilizing the architectural capabilities of the GPU. The optimization algorithm was tested with a MJPEG decoder, several benchmarks and synthetic graphs.

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