High-Speed Circuit Design Principles

2006 ◽  
pp. 74-1-74-24
Author(s):  
Stephen Long
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
Design Principles

scholarly journals Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios

2014 ◽  
Vol 2014 ◽  
pp. 1-20
Author(s):  
Bodhisatwa Sadhu ◽  
Martin Sturm ◽  
Brian M. Sadler ◽  
Ramesh Harjani
Keyword(s):  
Spectrum Sensing ◽  
Circuit Design ◽  
Software Defined Radio ◽  
High Speed ◽  
Cognitive Radios ◽  
Optimization Techniques ◽  
Switched Capacitor ◽  
Rf Receiver ◽  
Front End ◽  
5 Ghz

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates

2019 ◽  
Vol 28 (05) ◽  
pp. 1950079 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Umesh Ghanekar
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
High Performance ◽  
Single Layer ◽  
Memory Cell ◽  
Design Parameters ◽  
Flip Flop ◽  
Negative Edge ◽  
Wire Crossing ◽  
The Common

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[Formula: see text][Formula: see text]m2and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

Design and Test of High Speed Digitization Sampling Circuit Based on FPGA

2013 ◽  
Vol 482 ◽  
pp. 386-389
Author(s):  
Peng Qin ◽  
Hao Lu ◽  
Zhi Ye Jiang ◽  
Jin Liang Bai ◽  
Lu Gao ◽  
...  
Keyword(s):  
Data Acquisition ◽  
Circuit Design ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Engineering Practice ◽  
Excellent Performance ◽  
Field Programmable ◽  
High Speed Data Acquisition ◽  
High Speed Data ◽  
Data Acquisition Program

To sample wideband IF signal with large amounts of data, a high-speed data acquisition program is presented. The program focus on circuit design, issues that need attention, and high-speed sampling signal deceleration strategy. The 2.4GHz rate sampling data acquisition, reception and demux are completed with ADC083000 and Field-Programmable Gate Array (FPGA). At last, a result of sampling with the converter is offered by chipscope software. The result verified ADC083000 has an excellent performance with more than 6.5 bit ENOB and good phase coherence. In engineering practice, the design has been used and has good performance.

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