Reversible Realization of 4-Bit Vedic Multiplier Circuit with Optimized Performance Parameters

2019 ◽  
Vol 17 (10) ◽  
pp. 826-831
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
High Speed ◽  
Digital Circuit ◽  
Performance Parameters ◽  
Low Loss ◽  
Vital Part ◽  
Multiplication Process ◽  
Vedic Multiplier ◽  
Multiplier Circuit

Low power high speed calculating devices are foremost requirement of this era. Moreover, multiplication is considered as the most vital part of any calculating system. Multiplication process is generally considered as the speed limiting process as it requires more time as compared to other basic arithmetic calculations. So, here we focus on multiplication calculation using vedic method. Moreover, Reversible realization of any digital circuit improves the performance of the system by reducing the power loss from it. Here, the concept of vedic multiplication and Reversible approach are combined to propose a 4-bit multiplier circuit with optimized performance parameters. Proposed design is also analyzed and compared with existing designs. This approach may be employed to propose other low loss devices.

scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY

1995 ◽  
Vol 06 (01) ◽  
pp. 163-210 ◽  
Author(s):  
STEPHEN I. LONG
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Material Properties ◽  
High Speed ◽  
Digital Circuit ◽  
Bipolar Transistor ◽  
Clock Frequency ◽  
Digital Integrated Circuits ◽  
Heterojunction Devices ◽  
Circuit Technology

The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

scholarly journals Reversible Gate Logic Adder with Parity Preserving Design

2021 ◽  
Vol 1 (2) ◽  
Author(s):  
Kannadasan K
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Speed ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Main Challenge ◽  
Wide Range

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

scholarly journals Low Power 32 x 32 – bit Reversible Vedic Multiplier

2019 ◽  
Vol 8 (10) ◽  
pp. 852-856
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Reversible Logic ◽  
Low Power Consumption ◽  
Vedic Mathematics ◽  
Vedic Multiplier ◽  
X 32

Recently, low-power consuming devices are gaining demand due to excessive use and requirement of hand-held & portable electronic gadgets. The quest for designing better options to lower the power consumption of a device is in high-swing. The paper proposes two 32 x 32 – bit multipliers. The first design is based only on the Urdhava Tiryakbhyam Sutra of Vedic Mathematics. The use of this sutra has created a multiplier with higher throughput and lesser power utilization than conventional 32 x 32 – bit multipliers. The second design incorporates the reversible logic into the first design, which further reduces the power consumption of the system. Thus bringing together Vedic sutra for multiplication and reversible gates has led to the development of a Reversible Vedic Multiplier which has both the advantages of high-speed and low-power consumption.

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

A new design of a low-power reversible Vedic multiplier

2020 ◽  
Vol 18 (03) ◽  
pp. 2050002
Author(s):  
Meysam Rashno ◽  
Majid Haghparast ◽  
Mohammad Mosleh
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Reversible Logic ◽  
Arithmetic Circuits ◽  
Quantum Cost ◽  
Computing Systems ◽  
Vedic Multiplier ◽  
Wide Range ◽  
Logic Unit

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

scholarly journals Investigation on Low Power Digital Tree Multipliers

2020 ◽  
pp. 87-90
Author(s):  
Anitha P ◽  
Dhivya devi R ◽  
Siddharthraju K ◽  
Boobathi S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Complex Function ◽  
Processing System ◽  
Power Reduction ◽  
Signal Processing System ◽  
Delay Reduction ◽  
Is Implementation ◽  
Area Reduction ◽  
Vedic Multiplier

VLSI is the relating to more than one branch of science of utilizing the advanced semiconductor technology to develop various functional units of computational System. The most complex function carried out by ALU is multiplication. Digital multiplication is most extensively used operation particularly in signal processing, System designer has to sacrifice silicon die area in order to make the multiplication as soon as possible. In this paper, various multiplier architectures are simulated and compared with high speed and low power 8x8 Vedic multiplier (Urdhva Triyagbhayam) which uses modified carry select adder for partial product reduction. The design is implementation and simulation has been done by Microwind tool with 90 nm technology. The simulation result shows 58% of power reduction, 65% of delay reduction and 44% of area reduction has been attained.

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