Optimization Design of Low Power Consumption Kalman Filter Based on Field Programmable Gate Array

2016 ◽  
Vol 11 (6) ◽  
pp. 677-684 ◽  
Author(s):  
Lv Changzhi ◽  
Li Weikuo ◽  
Song Jun ◽  
Fan Di ◽  
Lu Xiushan
Keyword(s):  
Kalman Filter ◽  
Power Consumption ◽  
Low Power ◽  
Field Programmable Gate Array ◽  
Optimization Design ◽  
Low Power Consumption ◽  
Field Programmable ◽  
Gate Array

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

Nonvolatile Configuration Memory Cell for Low Power Field Programmable Gate Array

2011 ◽  
Author(s):  
Shinichi Yasuda ◽  
Kazutaka Ikegami ◽  
Tetsufumi Tanamoto ◽  
Atsuhiro Kinoshita ◽  
Keiko Abe ◽  
...  
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Memory Cell ◽  
Field Programmable ◽  
Gate Array

Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

2016 ◽  
Vol 10 (3) ◽  
pp. 163-172 ◽  
Author(s):  
Zarrin Tasnim Sworna ◽  
Mubin UlHaque ◽  
Nazma Tara ◽  
Hafiz Md. Hasan Babu ◽  
Ashis Kumar Biswas
Keyword(s):  
Low Power ◽  
Field Programmable Gate Array ◽  
Look Up Table ◽  
Field Programmable ◽  
Decimal Adder ◽  
Gate Array ◽  
Area Efficient

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rajasekar P. ◽  
Mangalam H.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Storage ◽  
Resource Sharing ◽  
Low Power Consumption ◽  
Multiplicative Inverse ◽  
Content Type ◽  
Field Programmable ◽  
Pipe Line ◽  
Affine Transforms

Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

scholarly journals Implementation of a number recognition algorithm built using a neural network on the BASYS3 FPGA panel

2021 ◽  
Vol 82 (4) ◽  
pp. 86-96
Author(s):  
A. A. Mukhanbet ◽  
◽  
E. S. Nurakhov ◽  
B. S. Daribayev ◽  
◽  
...  
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Low Power ◽  
Recognition Algorithm ◽  
Low Power Consumption ◽  
Portable Devices ◽  
Output Performance ◽  
Programmable Valve ◽  
Number Recognition ◽  
Field Programmable

In recent years, some field programmable valve arrays (FPGAs) based on CNN release phase accelerators have been introduced. FPGA is widely used in portable devices. They can be programmed to achieve higher concurrency and provide better performance. The power consumption of the FPGA is lower than that of GPUs with the same workload. These reasons make the FPGA suitable for implementing the CNN release phase. They can provide relative output performance for GPUs and achieve low power consumption, which is very important for portable devices. To effectively implement the CNN output phase on the FPGA, the design should have high parallelism, and the hardware resources used should be minimized to reduce the area and power consumption. In the process of working with the help of a neural network, an algorithm for recognizing handwritten numbers is implemented. A special architecture is being created to implement a neural network at the appatent level. The performance during operation and power consumption is comparable to the performance of the processor and the GPU.

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