scholarly journals Corrigendum to “PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability”

2018 ◽  
Vol 2018 ◽  
pp. 1-1
Author(s):  
O. Ahmed ◽  
S. Areibi ◽  
K. Chattha ◽  
B. Kelly
Keyword(s):  
Packet Classification ◽  
Classification Algorithm ◽  
Hardware Implementations ◽  
Incremental Update

scholarly journals PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

2011 ◽  
Vol 2011 ◽  
pp. 1-21 ◽  
Author(s):  
O. Ahmed ◽  
S. Areibi ◽  
K. Chattha ◽  
B. Kelly
Keyword(s):  
State Of The Art ◽  
Packet Classification ◽  
Classification Algorithm ◽  
Software Implementation ◽  
Network Services ◽  
Hardware Accelerator ◽  
Memory Consumption ◽  
Hardware Implementations ◽  
Speed Up ◽  
Incremental Update

Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor.

scholarly journals Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

2013 ◽  
Vol 2013 ◽  
pp. 1-33 ◽  
Author(s):  
O. Ahmed ◽  
S. Areibi ◽  
G. Grewal
Keyword(s):  
Packet Classification ◽  
Classification Algorithm ◽  
Hardware Accelerators ◽  
Instruction Set ◽  
Worst Case ◽  
Hardware Implementations ◽  
Fast Network ◽  
Rule Set ◽  
Application Specific ◽  
Case Classification

Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP) implementation and two pure Register-Transfer Level (RTL) implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on an Xeon processor.

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