scholarly journals Analysis of Conduction and Charging Mechanisms in Atomic Layer Deposited Multilayered HfO2/Al2O3 Stacks for Use in Charge Trapping Flash Memories

2018 ◽  
Vol 2018 ◽  
pp. 1-9 ◽  
Author(s):  
Nenad Novkovski ◽  
Albena Paskaleva ◽  
Aleksandar Skeparovski ◽  
Dencho Spassov
Keyword(s):  
Charge Trapping ◽  
Atomic Layer ◽  
Interface State ◽  
Limited Range ◽  
Flash Memories ◽  
High Permittivity ◽  
Voltage Range ◽  
Mos Structures

Method for characterization of electrical and trapping properties of multilayered high permittivity stacks for use in charge trapping flash memories is proposed. Application of the method to the case of multilayered HfO2/Al2O3 stacks is presented. By applying our previously developed comprehensive model for MOS structures containing high-κ dielectrics on the J-V characteristics measured in the voltage range without marked degradation and charge trapping (from −3 V to +3 V), several parameters of the structure connected to the interfacial layer and the conduction mechanisms have been extracted. We found that the above analysis gives precise information on the main characteristics and the quality of the injection layer. C-V characteristics of stressed (with write and erase pulses) structures recorded in a limited range of voltages between −1 V and +1 V (where neither significant charge trapping nor visible degradation of the structures is expected to occur) were used in order to provide measures of the effect of stresses with no influence of the measurement process. Both trapped charge and the distribution of interface states have been determined using modified Terman method for fresh structures and for structures stressed with write and erase cycles. The proposed method allows determination of charge trapping and interface state with high resolution, promising a precise characterization of multilayered high permittivity stacks for use in charge trapping flash memories.

Characterization of Wet Chemical Atomic Layer Etching of InGaAs

2021 ◽  
Vol 314 ◽  
pp. 95-98
Author(s):  
Tomoki Hirano ◽  
Kenya Nishio ◽  
Takashi Fukatani ◽  
Suguru Saito ◽  
Yoshiya Hagimoto ◽  
...  
Keyword(s):  
Surface Condition ◽  
Atomic Layer ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Etching Process ◽  
Wet Chemical ◽  
Oxide Removal ◽  
Atomic Layer Etching

In this work, we characterized the wet chemical atomic layer etching of an InGaAs surface by using various surface analysis methods. For this etching process, H2O2 was used to create a self-limiting oxide layer. Oxide removal was studied for both HCl and NH4OH solutions. Less In oxide tended to remain after the HCl treatment than after the NH4OH treatment, so the combination of H2O2 and HCl is suitable for wet chemical atomic layer etching. In addition, we found that repetition of this etching process does not impact on the oxide amount, surface roughness, and interface state density. Thus, nanoscale etching of InGaAs with no impact on the surface condition is possible with this method.

Electrical Characterization of High-k Dielectrics by Means of Flat-Band Voltage Transient Recording

2007 ◽  
Vol 996 ◽  
Author(s):  
Salvador Duenas ◽  
Helena Castán ◽  
Héctor García ◽  
Luis Bailón ◽  
Kaupo Kukli ◽  
...  
Keyword(s):  
Electric Fields ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Localized States ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Flat Band Voltage ◽  
High K ◽  
Mos Structures

AbstractWe have carried out a comparison between flat-band transients displayed in metal-oxide-semiconductor (MOS) structures fabricated on several atomic layer deposited (ALD) high-k dielectric films: HfO2, ZrO2, Al2O3, Ta2O5, TiO2, and Gd2O3. The gate voltage as a function of time is recorded while keeping constant the capacitance at the initial flat band condition (CFB). Since samples are in darkness, under no electric fields and no charge-injection conditions, transients must be due to charge trapping of localized states produced by electrons (holes) coming from the semiconductor by tunnelling. The process is assisted by phonons and it is therefore thermally activated. The temperature-transient amplitude relation follows an Arrhenius plot which provides the thermal activation energy of soft-optical phonons. Finally, we describe the dependencies of the flat-band voltage on the setup bias history (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) of the capacitance-voltage (C-V) characteristics of MOS structures.

Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

2013 ◽  
Vol 740-742 ◽  
pp. 691-694 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Flat Band ◽  
Mos Devices ◽  
State Densities ◽  
Mos Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011cm-2eV-1under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Accurate Characterization of Interface State Density of SiC MOS Structures and the Impacts on Channel Mobility

2014 ◽  
Vol 778-780 ◽  
pp. 418-423 ◽  
Author(s):  
Hironori Yoshioka ◽  
Takashi Nakamura ◽  
Junji Senzaki ◽  
Atsushi Shimozato ◽  
Yasunori Tanaka ◽  
...  
Keyword(s):  
Interface State ◽  
Interface States ◽  
State Density ◽  
Interface State Density ◽  
Subthreshold Slope ◽  
Field Effect Mobility ◽  
Channel Mobility ◽  
The Common ◽  
Mos Structures

We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.

Atomic Layer Deposition of Al2O3 Thin Films for Metal Insulator Semiconductor Applications on 4H-SiC

2016 ◽  
Vol 858 ◽  
pp. 685-688 ◽  
Author(s):  
Emanuela Schilirò ◽  
Salvatore di Franco ◽  
Patrick Fiorenza ◽  
Corrado Bongiorno ◽  
Hassan Gargouri ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Insulator ◽  
Metal Insulator ◽  
Layer Deposition ◽  
Capacitance Voltage ◽  
Mos Structures ◽  
Thermally Grown

This work reports on the growth and characterization of Al2O3 films on 4H-SiC, by Plasma Enhanced-Atomic Layer Deposition (PE-ALD). Different techniques were used to investigate the morphological, structural and electrical features of the Al2O3 films, both with and without the presence of a thin SiO2 layer, thermally grown on the 4H-SiC before ALD. Capacitance-voltage measurements on MOS structures resulted in a higher dielectric constant (ε~8.4) for the Al2O3/SiO2/SiC stack, with respect to that of the Al2O3/SiC sample (ε~ 6.7). Moreover, C<em>urrent density-Electric Field</em> measurements demonstrated a reduction of the leakage current and an improvement of the breakdown behaviour in the presence of the interfacial thermally grown SiO2. Basing on these preliminary results, possible applications of ALD-Al2O3 as gate insulator in 4H-SiC MOSFETs can be envisaged.

The Investigation of Fluorine Effects on Charge Trapping and Interface State Generation in Mos Structures

1991 ◽  
Vol 219 ◽  
Author(s):  
Dunxian D. Xie ◽  
Ta-Cheng Lin ◽  
Donald R. Young
Keyword(s):  
Charge Trapping ◽  
Interface State ◽  
Flat Band ◽  
Physical Damage ◽  
Mos Devices ◽  
Interface Charge ◽  
State Generation ◽  
Fluorinated Oxides ◽  
Donor States ◽  
Mos Structures

ABSTRACTThe bulk and interface charge trapping phenomena of fluorinated oxides have been studied by various electronic measurements. Fluorine is introduced into dry oxides by low energy (25kev) implantation followed by a 1000°C N2 ambient anneal to remove physical damage. Both the flat band and the mid gap voltage shifts of such MOS devices are measured during avalanche electron injection. We have developed techniques to separate effects due to interface state generation from bulk trapping effects. The bulk electron traps in the fluorinated oxides have a different cross section from the known water-related traps in conventional oxides. The generation of fast and slow interface states for different dosages of fluorine implantation is discussed based on Q-V and C-V measurements. The fast interface donor states, generated during avalanche injection, are charged at flat band but discharged at mid gap and beyond. An optimum dosage of fluorine implantation is found to suppress the so called turn-around effect during avalanche injection due to the formation of slow donor states. Finally, injection under high temperature (120°C-150°C) anneals out most of these donor states.

scholarly journals Characterization of SiO2/SiC Interface of Phosphorous-Doped MOS Capacitors by Conductance Measurements

2019 ◽  
Vol 8 (3) ◽  
pp. 5505-5508
Keyword(s):  
Frequency Response ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Channel Mobility ◽  
Conductance Method ◽  
Mos Structures

Interface states of MOS structures capacitors incorporated with low levels of phosphorous have been investigated by conductance and C-ψs method. The frequency response of interface states was observed by the conductance method up to 10 MHz. The correlation between the frequency response of interface states and interface state density determined by C-ψs method was studied. It was found that fast states in phosphorous incorporated samples reduced significantly at high frequency (>5 MHz) while sample annealed with nitrogen remained high up to 10 MHz. The interface state density, Dit of phosphorous incorporated sample near conduction band is lower compared to nitridated sample. These results indicate phosphorous passivation effectively reduces Dit at the SiO2 /SiC interfaces and can be correlated to high channel mobility.

Charge trapping and interface state generation in 6H-SiC MOS structures

1995 ◽  
Vol 28 (1-4) ◽  
pp. 197-200 ◽  
Author(s):  
V.V. Afanas'ev ◽  
M. Bassler ◽  
G. Pensl ◽  
M.J. Schulz
Keyword(s):  
Charge Trapping ◽  
Interface State ◽  
State Generation ◽  
Mos Structures

Characterization of Band Diagrams of Different Metal-SiO2-SiC(3C) Structures

2012 ◽  
Vol 711 ◽  
pp. 99-103 ◽  
Author(s):  
Krzysztof Piskorski ◽  
Henryk M. Przewlocki ◽  
Romain Esteve ◽  
Mietek Bakowski
Keyword(s):  
Measurement Techniques ◽  
Flat Band ◽  
Band State ◽  
Electric Parameters ◽  
Mos Structures

In this work the band diagrams of different MOS structures based on 3C-SiC substrate were determined. This has been achieved by application of many measurement techniques allowing determination of many electric parameters of the investigated structures. These parameters allowed to construct complete band diagrams which are demonstrated for two modes: for the flat-band state in the semiconductor and for the flat-band state in the dielectric.

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