scholarly journals Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

2018 ◽  
Vol 2018 ◽  
pp. 1-11 ◽  
Author(s):  
Lilia Kechiche ◽  
Lamjed Touil ◽  
Bouraoui Ouni
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Video Processing ◽  
Integrated Design ◽  
Processing System ◽  
Design Flow ◽  
System Level ◽  
Design Environment ◽  
Chip Design ◽  
On Chip

Driven by the importance of energy consumption in system-on-chip design as an evaluation factor, this paper presents a design methodology at the system level to optimize power consumption on ARM-based architecture for real-time video processing. The proposed design flow is based on the interaction between the tool and user optimizations. The tool optimizations are the options and best practices available on the integrated design environment for the Xilinx technology and the target Zynq-7000 architecture. The user methods present methods proposed by the user to optimize power consumption. We used the principles of voltage scaling and frequency scaling techniques for user methods. These two techniques allow energy to be consumed in the proportion of work to be done. The suggested flow is applied on real-time video processing system. The results show power savings for up to 60% with respect to performance and real-time constraints.

The Design of Real-Time and High-Speed Video Processing Platform for Aerial UAV Based on DM642

2014 ◽  
Vol 1061-1062 ◽  
pp. 1186-1189
Author(s):  
Ming Zhe Wei ◽  
Wan Wei Tang
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Speed ◽  
Rapid Development ◽  
Processing System ◽  
Video Signal ◽  
Good Effect ◽  
Time Data ◽  
Spatial Interference ◽  
On Chip

With the rapid development of aerial UAV (Unmanned Aerial Vehicle), the design of real-time data acquisition and transmission system for the video signal has a new applied field. It is different from traditional video acquisition and processing system, aerial video signal has the problems of screen jitter and spatial interference. The processing algorithm of aerial UAV airborne video signal is put forward in the paper, and the platform of high speed procession is constructed based on chip TMS320DM642, and get a good effect.

Design of a real-time video processing system with FPGA

2002 ◽  
Author(s):  
Wei Liu ◽  
Zeying Chi ◽  
Wenjian Chen
Keyword(s):  
Real Time ◽  
Video Processing ◽  
Processing System

Parallel-Pipelined Video Processing in Multicore Heterogeneous Systems on Chip

2021 ◽  
Vol 26 (2) ◽  
pp. 172-183
Author(s):  
E.S. Yanakova ◽  
◽  
G.T. Macharadze ◽  
L.G. Gagarina ◽  
A.A. Shvachko ◽  
...  
Keyword(s):  
Video Processing ◽  
High Efficiency ◽  
Heterogeneous Systems ◽  
Video Data ◽  
System Level ◽  
Video Information ◽  
Systems On Chip ◽  
The Face ◽  
Parallel Pipelined ◽  
On Chip

A turn from homogeneous to heterogeneous architectures permits to achieve the advantages of the efficiency, size, weight and power consumption, which is especially important for the built-in solutions. However, the development of the parallel software for heterogeneous computer systems is rather complex task due to the requirements of high efficiency, easy programming and the process of scaling. In the paper the efficiency of parallel-pipelined processing of video information in multiprocessor heterogeneous systems on a chip (SoC) such as DSP, GPU, ISP, VDP, VPU and others, has been investigated. A typical scheme of parallel-pipelined processing of video data using various accelerators has been presented. The scheme of the parallel-pipelined video data on heterogeneous SoC 1892VM248 has been developed. The methods of efficient parallel-pipelined processing of video data in heterogeneous computers (SoC), consisting of the operating system level, programming technologies level and the application level, have been proposed. A comparative analysis of the most common programming technologies, such as OpenCL, OpenMP, MPI, OpenAMP, has been performed. The analysis has shown that depend-ing on the device finite purpose two programming paradigms should be applied: based on OpenCL technology (for built-in system) and MPI technology (for inter-cell and inter processor interaction). The results obtained of the parallel-pipelined processing within the framework of the face recognition have confirmed the effectiveness of the chosen solutions.

Reconfigurable distributed real-time processing for multi-robot control: Design, implementation and experimentation

Robotica ◽  
2004 ◽  
Vol 22 (6) ◽  
pp. 661-679 ◽  
Author(s):  
J. Z. Pan ◽  
R. V. Patel
Keyword(s):  
Real Time ◽  
Information Exchange ◽  
Robot Control ◽  
Data Exchange ◽  
Processing System ◽  
System Level ◽  
Layered System ◽  
Test Bed ◽  
Design And Implementation ◽  
Multi Robot

Sophisticated robotic applications require systems to be reconfigurable at the system level. Aiming at this requirement, this paper presents the design and implementation of a software architecture for a reconfigurable real-time multi-processing system for multi-robot control. The system is partitioned into loosely coupled function units and the data modules manipulated by the function units. Modularized and unified structures of the sub-controllers and controller processes are designed and constructed. All the controller processes run autonomously and intra-sub-controller information exchange is realized by shared data modules that serve as a data repository in the sub-controller. The dynamic data-management processes are responsible for data exchange among sub-controllers and across the computer network. Among sub-controllers there is no explicit temporal synchronization and the data dependencies are maintained by using datum-based synchronization. The hardware driver is constructed as a two-layered system to facilitate adaptation to various robotic hardware systems. A series of effective schemes for software fault detection, fault anticipation and fault termination are accomplished to improve run-time safety. The system is implemented cost-effectively on a QNX real-time operating system (RTOS) based system with a complete PC architecture, and experimentally validated successfully on an experimental dual-arm test-bed. The results indicate that the architectural design and implementation are well suited for advanced application tasks.

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