scholarly journals An Alternative Approach Obtaining a Normalization Factor in Normalized Min-Sum Algorithm for Low-Density Parity-Check Code

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
In-Woo Yun ◽  
Hee-ran Lee ◽  
Joon Tae Kim

The min-sum algorithm (MSA) for decoding Low-Density Parity-Check (LDPC) code is an approximation algorithm that can greatly reduce the computational complexity of the belief propagation algorithm (BPA). To reduce the error between MSA and BPA, an improved MSA such as normalized min-sum algorithm (NMSA) that uses the normalization factor when updating the check node is used in many LDPC decoders. When obtaining an optimal normalization factor, density evolution (DE) is usually used. However, not only does the DE method require a large number of calculations, it may not be optimal for obtaining a normalization factor due to the theoretical assumptions that need to be satisfied. This paper proposes a new method obtaining a normalization factor for NMSA. We first examine the relationship between the minimum value of variable node messages’ magnitudes and the magnitudes of check node outputs of BPA using the check node message distribution (CMD) chart. And then, we find a normalization factor that minimizes the error between the magnitudes of check node output of NMSA and BPA. We use the least square method (LSM) to minimize the error. Simulation on ATSC 3.0 LDPC codes demonstrates that the normalization factor obtained by this proposed method shows better decoding performance than the normalization factor obtained by DE.

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.


2013 ◽  
Vol 347-350 ◽  
pp. 1864-1867
Author(s):  
Ning Hao ◽  
Yang An Zhang ◽  
Jin Nan Zhang ◽  
Ming Lun Zhang ◽  
Xue Guang Yuan

Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.


2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family


2012 ◽  
Author(s):  
Ierwan Ab. Karim ◽  
Abdul Karem Hussein Mohammed Almawgani ◽  
Mohd Fadzli Mohd Salleh

Dalam kertas ini prestasi kod ketumpatan–rendah kesetaratan–semak (LDPC) dan kod Reed–Solomon (RS) telah dianalisis dengan menggunakan sistem penghantaran imej tanpa wayar. Sistem ini menggunakan salur penambahan Gaussian hinggar putih (AWGN). Dalam kerja ini, imej kelabu telah telah digunakan sebagai punca kemasukan daya. Kualiti imej kelabu yang dibina semula selepas saluran penyahkodan adalah diukur dengan menggunakan puncak nisbah isyarat–hinggar (PSNR) dengan membandingkan imej yang dibina semula dengan kemasukan imej asal. Keputusan penyelakuan menunjukkan prestasi sistem penghantaran imej dengan menggunakan kod LDPC sentiasa mengatasi prestasi sistem yang menggunakan kod RS dalam salur AWGN. Kualiti keluaran imej kelabu adalah dianggap bagus sekiranya nilai PSNR melebihi 30 dB. Kata kunci: Sistem penghantaran imej tanpa wayar; kod LDPC; kod Reed Solomon; salur AGWN In this paper the performance of Low–Density Parity–Check (LDPC) and Reed–Solomon (RS) codes are analyzed using a wireless image transmission system. The system utilizes the Additive White Gaussian Noise (AWGN) channel. In this work, a grayscale image is used as the input data source. The quality of the reconstructed grayscale image after the channel decoder is measured using the Peak Signal to Noise Ratio (PSNR) by comparing the reconstructed image with the input grayscale image. Simulation results show that the performance of image transmission system using LDPC code is always outperformed the system with RS code in AWGN channel. The quality of output grayscale image is considered good if the value of the PSNR is above 30 dB. Key words: Wiresless image transmission system; LDPC code; Reed Solomon code; AWGN channel


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