scholarly journals Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

2017 ◽  
Vol 2017 ◽  
pp. 1-8
Author(s):  
Satheesh Bojja Venkatakrishnan ◽  
Elias A. Alwan ◽  
John L. Volakis
Keyword(s):  
Clock Synchronization ◽  
Digital Signal ◽  
Data Converter ◽  
Analog To Digital ◽  
Synchronization Errors ◽  
Digital To Analog Converters ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Signal Synchronization ◽  
Signal Processors

Typical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications

2018 ◽  
Vol 7 (1) ◽  
pp. 1
Author(s):  
M. Parvathi ◽  
N. Vasantha ◽  
K. Satya Prasad
Keyword(s):  
Systems Design ◽  
Digital Signal ◽  
Low Area ◽  
Gate Arrays ◽  
Current Limit ◽  
Maximum Current ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Layout Area ◽  
Signal Processors

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

The Characters of Dual Harmonic Frames of Subspaces and Applications in Signal Processing Theory

2013 ◽  
Vol 457-458 ◽  
pp. 731-735
Author(s):  
Yong Yi Huang ◽  
Jian Feng Zhou
Keyword(s):  
Signal Processing ◽  
Information Science ◽  
Digital Signal ◽  
General Purpose ◽  
Decomposition Scheme ◽  
Processing Theory ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Definition Of ◽  
Signal Processors

Digital signal processing is the processing of digitized discrete-time samp-led signals. Processing is done by general-purpose computers or by digital circuits such as ASICs, field-programmable gate arrays or specialized digital signal processors. Information science focuses on understanding problems from the perspective of the stakeholders involved and then applying information and other technologies as needed. The definition of multiple pseudofames for subspaces with integer translation is proposed. The notion of a generalized multiresolution structure (GMS) of is also introduced. The construction of a generalized multiresolution structure of Paley-Wiener subspaces of is investigated. The pyramid decomposition scheme is derived based on a generalized multiresolution structure.

Designing Discrete and Digital Communication Systems

2021 ◽  
pp. 542-561
Author(s):  
Stevan Berber
Keyword(s):  
Communication Systems ◽  
Digital Signal ◽  
Clear Understanding ◽  
Gate Arrays ◽  
Advantages And Disadvantages ◽  
Shift Keying ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Signal Processors ◽  
The Relationship

In this chapter, the practical aspects of the design of digital discrete communication systems, primarily digital signal processors and field -programmable gate arrays, are analysed. The systems are presented at the level of block schematics, to address the main issues in their design and discuss the advantages and disadvantages of various designs in digital technology. Designs using quadriphase-shift keying and quadrature amplitude modulation are presented separately. The operation of each system is explained in terms of the theoretical structure of the system, which allows a clear understanding of the relationship between the theoretical model of the system and its practical design. The structures of the first, second, and third generation of discrete transceiver designs are presented and discussed.

BLOCK FLOATING POINT FFT IMPLEMENTATION FOR DMT xDSL SYSTEMS

2004 ◽  
Vol 13 (05) ◽  
pp. 1147-1164
Author(s):  
Th. ZAHARIADIS ◽  
S. APOSTOLACOS ◽  
I. GRAMMATIKAKIS ◽  
D. MEXIS ◽  
N. ZERVOS ◽  
...  
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Digital Signal ◽  
Floating Point ◽  
Digital Subscriber Line ◽  
Discrete Multitone ◽  
Field Programmable ◽  
Signal Processing Algorithms ◽  
Programmable Gate Arrays ◽  
Signal Processors

The development of multiple Discrete Multitone (DMT) Digital Subscriber Line (DSL) flavors on a single platform can benefit considerably by a programmable architecture, which feature Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), especially when fast prototyping is targeted. However, the flexibility assumed to be offered by algorithmic partitioning does not automatically and proportionally simplify the digital signal processing algorithms, unless the effects of overflow/saturation in intermediate processing stages are carefully studied. The effects of overflow/saturation in intermediate stages is very critical throughout the design process, since the operations involved are nonlinear in nature and affect the most significant bits of the computational process. This paper presents an efficient soft-core implementation of a Block Floating Point FFT (BLFP) algorithm, designed for a Very high-speed DSL (VDSL) DMT systems and for the full variety of other xDSL DMT flavors, as the latter demand an extended dynamic range to achieve performance that may otherwise be only warranted by costly floating-point chip implementations.

scholarly journals Multiple Harmonics Fitting Algorithms Applied to Periodic Signals Based on Hilbert-Huang Transform

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Hui Wang ◽  
Zhengshi Liu ◽  
Bin Zhu ◽  
Quanjun Song
Keyword(s):  
Signal Processing ◽  
Harmonic Distortion ◽  
Digital Signal ◽  
Periodic Signal ◽  
Sinusoidal Wave ◽  
Analog To Digital ◽  
Triangular Wave ◽  
Hilbert Huang Transform ◽  
Digital To Analog Converters ◽  
Periodic Signals

A new generation of multipurpose measurement equipment is transforming the role of computers in instrumentation. The new features involve mixed devices, such as kinds of sensors, analog-to-digital and digital-to-analog converters, and digital signal processing techniques, that are able to substitute typical discrete instruments like multimeters and analyzers. Signal-processing applications frequently use least-squares (LS) sine-fitting algorithms. Periodic signals may be interpreted as a sum of sine waves with multiple frequencies: the Fourier series. This paper describes a new sine fitting algorithm that is able to fit a multiharmonic acquired periodic signal. By means of a “sinusoidal wave” whose amplitude and phase are both transient, the “triangular wave” can be reconstructed on the basis of Hilbert-Huang transform (HHT). This method can be used to test effective number of bits (ENOBs) of analog-to-digital converter (ADC), avoiding the trouble of selecting initial value of the parameters and working out the nonlinear equations. The simulation results show that the algorithm is precise and efficient. In the case of enough sampling points, even under the circumstances of low-resolution signal with the harmonic distortion existing, the root mean square (RMS) error between the sampling data of original “triangular wave” and the corresponding points of fitting “sinusoidal wave” is marvelously small. That maybe means, under the circumstances of any periodic signal, that ENOBs of high-resolution ADC can be tested accurately.

An Undergraduate Course and Laboratory in Digital Signal Processing With Field Programmable Gate Arrays

2010 ◽  
Vol 53 (4) ◽  
pp. 638-645 ◽  
Author(s):  
Uwe Meyer-Base ◽  
Alonzo Vera ◽  
Anke Meyer-Base ◽  
Marios S. Pattichis ◽  
Reginald J. Perry
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

scholarly journals Comparison of reconfigurable structures for flexible word-length multiplication

2008 ◽  
Vol 6 ◽  
pp. 113-118 ◽  
Author(s):  
O. A. Pfänder ◽  
R. Nopper ◽  
H.-J. Pfleiderer ◽  
S. Zhou ◽  
A. Bermak
Keyword(s):  
Power Dissipation ◽  
Word Length ◽  
Digital Signal ◽  
Gate Arrays ◽  
Computing Unit ◽  
Field Programmable ◽  
Embedded Blocks ◽  
Programmable Gate Arrays ◽  
Array Structures ◽  
Reconfigurable Structures

Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

scholarly journals A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1116 ◽  
Author(s):  
Yushkova ◽  
Sanchez ◽  
de Castro ◽  
Martínez-García
Keyword(s):  
High Speed ◽  
Hardware In The Loop ◽  
Low Speed ◽  
Digital To Analog Converters ◽  
Gate Arrays ◽  
Simulation Techniques ◽  
Input Signals ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Input Waveform

The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.

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