scholarly journals Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

2017 ◽  
Vol 2017 ◽  
pp. 1-13 ◽  
Author(s):  
Hang Song ◽  
Afreen Azhari ◽  
Xia Xiao ◽  
Eiji Suematsu ◽  
Hiromasa Watanabe ◽  
...  

A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS) integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T) switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.


1987 ◽  
Vol 96 (1_suppl) ◽  
pp. 76-79
Author(s):  
J. Génin ◽  
R. Charachon

In a multichannel cochlear prosthesis, electrical interactions between electrodes impose severe limitations on dynamic range and selectivity. We present a theoretical model to cope with these limitations. Building a successful cochlear implant requires full custom-integrated circuits. We present the design of such a device, implemented in complementary metal oxide semiconductor technology. The area of the chip is 9 mm2 and it can stimulate 15 cochlear electrodes with current impulses.


2020 ◽  
Author(s):  
Brian Redman

This paper is a follow-up to three previous papers: the first introducing the new Bitstream Photon Counting Chirped Amplitude Modulation (AM) Lidar (PC-CAML) with the unipolar Digital Logic Local Oscillator (DLLO) concept, the second introducing the improvement thereof using the bipolar DLLO, and the third introducing the improvement of digital In-phase and Quadrature-phase (I/Q) demodulation.In that previous work, the signal was a single unipolar chirped sinusoidal or square wave. This paper introduces a new bitstream PC-CAML transceiver architecture that combines two unipolar chirped signals, referred to as the dual unipolar signal, to form a single bipolar signal in the receiver. (patent pending) This bipolar signal is mixed with the bipolar DLLOs in the in-phase (I) digital mixing and quadrature-phase (Q) digital mixing channels for digital I/Q demodulation for improved signal-to-noise ratio (SNR) compared to that when using a single unipolar signal.The simulation results presented in this paper indicate an SNR improvement for the dual unipolar chirped sinusoidal signal bitstream PC-CAML compared to that of the unipolar chirped sinusoidal signal bitstream PC-CAML (both with bipolar DLLOs and digital I/Q demodulation) of from about 3 dB to about 6 dB for signals below the onset of receiver saturation, and an improvement for maximum achievable SNR of about 13 dB if the receiver is allowed to saturate.The bitstream PC-CAML with a dual unipolar signal and bipolar DLLOs with digital I/Q demodulation architecture discussed in this paper adds complexity to the transmitter and receiver compared to the architectures presented in the previous papers. Whether or not this additional complexity is worth the improved SNR will have to be decided as part of system trade studies for particular systems and their applications.However, the new architecture still retains the key advantages of the previous bitstream PC-CAML architectures since it still replaces bulky, power-hungry, and expensive wideband RF analog electronics in the receiver with digital components that can be implemented in inexpensive silicon complementary metal-oxide-semiconductor (CMOS) read-out integrated circuits (ROICs) to make the bitstream PC-CAML with a DLLO more suitable for compact lidar-on-a-chip systems and lidar array receivers than previous standard PC-CAML systems.This paper introduces the dual unipolar signal and bipolar DLLOs with digital I/Q demodulation transceiver architecture for bitstream PC-CAML, and presents the initial SNR theory with comparisons to Monte Carlo simulation results.


2017 ◽  
Vol 12 (1) ◽  
pp. 33-41
Author(s):  
Vinicius Vono Peruzzi ◽  
Christian Renaux ◽  
Denis Flandre ◽  
Salvador Pinillos Gimenez

This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.


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