scholarly journals High Frequency InGaAs MOSFET with Nitride Sidewall Design for Low Power Application

2017 ◽  
Vol 2017 ◽  
pp. 1-9
Author(s):  
Jiongjiong Mo ◽  
Hua Chen ◽  
Zhiyu Wang ◽  
Faxin Yu
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Frequency ◽  
Current Problem ◽  
Device Simulation ◽  
Parasitic Capacitance ◽  
Thermal Budget ◽  
Drain Side ◽  
Power Application ◽  
Ingaas Mosfet

InxGa1-xAsdevices have been widely researched for low power high frequency applications due to the outstanding electron mobility and small bandgap of the materials. Regrown source/drain technology is highly appreciated in InGaAs MOSFET, since it is able to reduce the thermal budget induced by ion implantation, as well as reduce the source/drain resistance. However, regrown source/drain technology has problems such as high parasitic capacitance and high electric field at gate edge towards the drain side, which will lead to large drain leakage current and compromise the frequency performance. To alleviate the drain leakage current problem for low power applications and to improve the high frequency performance, a novel Si3N4sidewall structure was introduced to the InGaAs MOSFET. Device simulation was carried out with different newly proposed sidewall designs. The results showed that both the drain leakage current and the source/drain parasitic capacitance were reduced by applying Si3N4sidewall together with InP extended layer in InGaAs MOSFET. The simulation results also suggested that the newly created “recessed” sidewall was able to bring about the most frequency favorable characteristic with no current sacrifice.

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY

2013 ◽  
Vol 12 (06) ◽  
pp. 1350042
Author(s):  
ANUJ KUMAR SHRIVASTAVA ◽  
SHYAM AKASHE
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Full Adder ◽  
Basic Block ◽  
Double Gate ◽  
Arithmetic Circuit ◽  
Double Gate Mosfet ◽  
Rf Devices ◽  
Power Application ◽  
Circuit Technique

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

scholarly journals Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

2020 ◽  
Vol 8 (5) ◽  
pp. 3361-3366
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Research Work ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Pvt Variations ◽  
Power Application ◽  
Subthreshold Operation ◽  
Near Threshold

With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.

scholarly journals Common-Ground Photovoltaic Inverters for Leakage Current Mitigation: Comparative Review

2021 ◽  
Vol 11 (23) ◽  
pp. 11266
Author(s):  
Mahmoud A. Gaafar ◽  
Mohamed Orabi ◽  
Ahmed Ibrahim ◽  
Ralph Kennel ◽  
Mohamed Abdelrahem
Keyword(s):  
Leakage Current ◽  
Performance Indicators ◽  
High Frequency ◽  
Common Ground ◽  
Parasitic Capacitance ◽  
Pv Systems ◽  
Advantages And Disadvantages ◽  
Comparative Review ◽  
Grid Side ◽  
The Cost

In photovoltaic systems, parasitic capacitance is often formed between PV panels and the ground. Because of the switching nature of PV converters, a high-frequency voltage is usually generated over these parasitic capacitances; this, in turn, can result in a common-mode current known as leakage current. This current can badly reach a high value if a resonance circuit is excited through the PV’s parasitic capacitance and the converter’s inductive components. Transformers are usually used for leakage current mitigation. However, this decreases the efficiency and increases the cost, size, and weight of the PV systems. Number of strategies have been introduced to mitigate the leakage current in transformer-less converters. Among these strategies, using common-ground converters is considered the most effective solution as it offers a solid connection between the negative terminal of PV modules and the neutral of the grid side; thus, complete mitigation of the leakage current is achieved. Number of common-ground inverters have been recently presented. These inverters are different in their size, cost, boosting capability, the possibility of producing DC currents, and their capability to offer multilevel shaping of output voltage. This work introduces a comprehensive review and classification for various common-ground PV inverters. Therefore, a clear picture of the advantages and disadvantages of these inverters is clarified. This provides a useful indication for a trade-off between gaining some of the advantages and losing others in PV systems. In addition, the potentials for optimization based on different performance indicators are identified.

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