scholarly journals Efficient Thread Mapping for Heterogeneous Multicore IoT Systems

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Thomas Mezmur Birhanu ◽  
Zhetao Li ◽  
Hiroo Sekiya ◽  
Nobuyoshi Komuro ◽  
Young-June Choi
Keyword(s):  
Time Complexity ◽  
Multicore Systems ◽  
Thread Scheduling ◽  
Mapping Algorithm ◽  
Heterogeneous Multicore ◽  
Heterogeneous Architectures ◽  
Cpu Utilization ◽  
Speed Up ◽  
Thread Mapping

This paper proposes a thread scheduling mechanism primed for heterogeneously configured multicore systems. Our approach considers CPU utilization for mapping running threads with the appropriate core that can potentially deliver the actual needed capacity. The paper also introduces a mapping algorithm that is able to map threads to cores in anO(N log M)time complexity, whereNis the number of cores andMis the number of types of cores. In addition to that we also introduced a method of profiling heterogeneous architectures based on the discrepancy between the performances of individual cores. Our heterogeneity aware scheduler was able to speed up processing by 52.62% and save power by 2.22% as compared to the CFS scheduler that is a default in Linux systems.

scholarly journals Offload – Automating Code Migration to Heterogeneous Multicore Systems

2010 ◽  
pp. 337-352 ◽  
Author(s):  
Pete Cooper ◽  
Uwe Dolinsky ◽  
Alastair F. Donaldson ◽  
Andrew Richards ◽  
Colin Riley ◽  
...  
Keyword(s):  
Multicore Systems ◽  
Heterogeneous Multicore ◽  
Code Migration

On the General Class of Models of Adiabatic Evolution

2016 ◽  
Vol 23 (03) ◽  
pp. 1650016 ◽  
Author(s):  
Jie Sun ◽  
Songfeng Lu ◽  
Fang Liu
Keyword(s):  
Ground State ◽  
General Class ◽  
Time Complexity ◽  
State Energy ◽  
Search Problem ◽  
Quantum Search ◽  
Final States ◽  
Adiabatic Evolution ◽  
Speed Up ◽  
Effective Use

The general class of models of adiabatic evolution was proposed to speed up the usual adiabatic computation in the case of quantum search problem. It was shown [8] that, by temporarily increasing the ground state energy of a time-dependent Hamiltonian to a suitable quantity, the quantum computation can perform the calculation in time complexity O(1). But it is also known that if the overlap between the initial and final states of the system is zero, then the computation based on the generalized models of adiabatic evolution can break down completely. In this paper, we find another severe limitation for this class of adiabatic evolution-based algorithms, which should be taken into account in applications. That is, it is still possible that this kind of evolution designed to deal with the quantum search problem fails completely if the interpolating paths in the system Hamiltonian are chosen inappropriately, while the usual adiabatic evolutions can do the same job relatively effectively. This implies that it is not always recommendable to use nonlinear paths in adiabatic computation. On the contrary, the usual simple adiabatic evolution may be sufficient for effective use.

scholarly journals Worst-case energy consumption minimization based on interference analysis and bank mapping in multicore systems

2017 ◽  
Vol 13 (2) ◽  
pp. 155014771668696
Author(s):  
Zhihua Gan ◽  
Zhimin Gu ◽  
Hai Tan ◽  
Mingquan Zhang ◽  
Jizan Zhang
Keyword(s):  
Energy Consumption ◽  
Real Time ◽  
Multicore Systems ◽  
Worst Case ◽  
Mapping Algorithm ◽  
Fine Grained ◽  
Energy Consumption Reduction ◽  
Deadline Constraints ◽  
Core Mapping ◽  
The Impact

Energy is a scarce resource in real-time embedded systems due to the fact that most of them run on batteries. Hence, the designers should ensure that the energy constraints are satisfied in addition to the deadline constraints. This necessitates the consideration of the impact of the interference due to shared, low-level hardware resources such as the cache on the worst-case energy consumption of the tasks. Toward this aim, this article proposes a fine-grained approach to analyze the bank-level interference (bank conflict and bus access interference) on real-time multicore systems, which can reasonably estimate runtime interferences in shared cache and yield tighter worst-case energy consumption. In addition, we develop a bank-to-core mapping algorithm for reducing bank-level interference and improving the worst-case energy consumption. The experimental results demonstrate that our approach can improve the tightness of worst-case energy consumption by 14.25% on average compared to upper-bound delay approach. The bank-to-core mapping provides significant benefits in worst-case energy consumption reduction with 7.23%.

Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems

2011 ◽  
Vol 71 (1) ◽  
pp. 114-131 ◽  
Author(s):  
Juan Carlos Saez ◽  
Daniel Shelepov ◽  
Alexandra Fedorova ◽  
Manuel Prieto
Keyword(s):  
Multicore Systems ◽  
Heterogeneous Multicore

scholarly journals Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Program Inputs

2021 ◽  
Vol 20 (6) ◽  
pp. 1-35
Author(s):  
Junio Cezar Ribeiro Da Silva ◽  
Lorena Leão ◽  
Vinicius Petrucci ◽  
Abdoulaye Gamatié ◽  
Fernando Magno Quintão Pereira
Keyword(s):  
Linear Regression ◽  
Heterogeneous System ◽  
Multivariate Linear Regression ◽  
Statistical Regression ◽  
Efficient Tool ◽  
Heterogeneous Multicore ◽  
Heterogeneous Architectures ◽  
Java Bytecode ◽  
Hardware Configuration ◽  
Adaptive Compilation

A hardware configuration is a set of processors and their frequency levels in a multicore heterogeneous system. This article presents a compiler-based technique to match functions with hardware configurations. Such a technique consists of using multivariate linear regression to associate function arguments with particular hardware configurations. By showing that this classification space tends to be convex in practice, this article demonstrates that linear regression is not only an efficient tool to map computations to heterogeneous hardware, but also an effective one. To demonstrate the viability of multivariate linear regression as a way to perform adaptive compilation for heterogeneous architectures, we have implemented our ideas onto the Soot Java bytecode analyzer. Code that we produce can predict the best configuration for a large class of Java and Scala benchmarks running on an Odroid XU4 big.LITTLE board; hence, outperforming prior techniques such as ARM’s GTS and CHOAMP, a recently released static program scheduler.

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