scholarly journals Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences

2016 ◽  
Vol 2016 ◽  
pp. 1-9 ◽  
Author(s):  
Iljung Yoon ◽  
Heewon Joung ◽  
Jooheung Lee
Keyword(s):  
Edge Detection ◽  
Embedded System ◽  
Real Time ◽  
Video Sequences ◽  
Density Level ◽  
Real Time Processing ◽  
Reconfigurable System ◽  
Video Frames ◽  
Noise Density ◽  
Run Time

We implement Zynq-based self-reconfigurable system to perform real-time edge detection of 1080p video sequences. While object edge detection is a fundamental tool in computer vision, noises in the video frames negatively affect edge detection results significantly. Moreover, due to the high computational complexity of 1080p video filtering operations, hardware implementation on reconfigurable hardware fabric is necessary. Here, the proposed embedded system utilizes dynamic reconfiguration capability of Zynq SoC so that partial reconfiguration of different filter bitstreams is performed during run-time according to the detected noise density level in the incoming video frames. Pratt’s Figure of Merit (PFOM) to evaluate the accuracy of edge detection is analyzed for various noise density levels, and we demonstrate that adaptive run-time reconfiguration of the proposed filter bitstreams significantly increases the accuracy of edge detection results while efficiently providing computing power to support real-time processing of 1080p video frames. Performance results on configuration time, CPU usage, and hardware resource utilization are also compared.

scholarly journals SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

2021 ◽  
Vol 10 (3) ◽  
pp. 237
Author(s):  
Matias Javier Oliva ◽  
Pablo Andrés García ◽  
Enrique Mario Spinelli ◽  
Alejandro Luis Veiga
Keyword(s):  
Embedded System ◽  
Real Time ◽  
General Purpose ◽  
System Response ◽  
Single Chip ◽  
Real Time Processing ◽  
General Purpose Processor ◽  
Time Operation ◽  
Electroencephalographic Signals ◽  
High Level

<span lang="EN-US">Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.</span>

scholarly journals Real-Time Moving Object Detection in High-Resolution Video Sensing

Sensors ◽  
2020 ◽  
Vol 20 (12) ◽  
pp. 3591 ◽  
Author(s):  
Haidi Zhu ◽  
Haoran Wei ◽  
Baoqing Li ◽  
Xiaobing Yuan ◽  
Nasser Kehtarnavaz
Keyword(s):  
High Resolution ◽  
Object Detection ◽  
Real Time ◽  
Moving Object Detection ◽  
Moving Object ◽  
Computationally Efficient ◽  
Real Time Processing ◽  
Time Processing ◽  
Video Frames ◽  
High Resolution Images

This paper addresses real-time moving object detection with high accuracy in high-resolution video frames. A previously developed framework for moving object detection is modified to enable real-time processing of high-resolution images. First, a computationally efficient method is employed, which detects moving regions on a resized image while maintaining moving regions on the original image with mapping coordinates. Second, a light backbone deep neural network in place of a more complex one is utilized. Third, the focal loss function is employed to alleviate the imbalance between positive and negative samples. The results of the extensive experimentations conducted indicate that the modified framework developed in this paper achieves a processing rate of 21 frames per second with 86.15% accuracy on the dataset SimitMovingDataset, which contains high-resolution images of the size 1920 × 1080.

scholarly journals An Application based Efficient Thread Level Parallelism Scheme on Heterogeneous Multicore Embedded System for Real Time Image Processing.

2020 ◽  
Vol 21 (1) ◽  
pp. 47-56
Author(s):  
K Indragandhi ◽  
Jawahar P K
Keyword(s):  
Image Processing ◽  
Edge Detection ◽  
Embedded System ◽  
Real Time ◽  
Execution Time ◽  
Image Size ◽  
Multicore Processor ◽  
Detection Scheme ◽  
Thread Level Parallelism ◽  
Level Parallelism

The recent advent of the embedded devices is equipped with multicore processor as it significantly improves the system performance. In order to utilize all the core in multicore processor in an efficient manner, application programs need to be parallelized. An efficient thread level parallelism (ETLP) scheme is proposed in this paper and uses computationally intensive edge detection algorithm for evaluation. Edge detection is the important process in various real time applications namely vehicle detection in traffic control, medical image processing etc. The main objective of ETLP scheme is to reduce the execution time and increase the CPU core utilization. The performance of ETLP scheme is evaluated with basic edge detection scheme (BEDS) for different image size. The experimental results reveal that the proposed ETLP scheme achieves efficiency of 49% and 72% for the image size 300 x 256 and 1024 x 1024 respectively. Furthermore an ETLP scheme reducing 66% execution time for image size 1024 x 1024 when compared with BEDS.

Embedded Realization of a Adaptive Threshold Edge Detection Base on Canny Operator

2014 ◽  
Vol 543-547 ◽  
pp. 2766-2769 ◽  
Author(s):  
Cheng Po Mu ◽  
Qing Xian Dong ◽  
Jie Lian ◽  
Ming Song Peng
Keyword(s):  
Image Processing ◽  
Edge Detection ◽  
Data Processing ◽  
Embedded System ◽  
Real Time ◽  
Adaptive Threshold ◽  
Processing Technology ◽  
Embedded Image Processing ◽  
Image Processing Technology ◽  
Embedded Image

Edge detection that is an important means to realize image segmentation has important application significance in image processing, industrial detection, artificial intelligence and the target recognition field. As the demand for real-time and rapidity in image processing, the embedded image processing technology has been widely applied. But the realization of real-time edge detection for image requires a large amount of data processing, limited system resources of embedded system is the main reason of the embedded image processing technology development. In order to shorten time embedded systems edge detection processing large amounts of data, based on adaptive threshold Canny algorithm, this paper as the FPGA data processing DSP chips and made a FPGA + DSP hardware architecture, effectively improve the system real-time, get a good edge detection results.

Design of Virtual Oscilloscope Based on S3C2410

2011 ◽  
Vol 189-193 ◽  
pp. 227-230
Author(s):  
Shu Lin Shi ◽  
Guo Rui Pi
Keyword(s):  
Embedded System ◽  
Real Time ◽  
High Speed ◽  
Data Exchange ◽  
Control Logic ◽  
Real Time Processing ◽  
High Speed Data ◽  
The Common ◽  
The Embedded System ◽  
The Cost

: This topic has designed a kind of virtual oscilloscope based on the embedded technical. On the hardware the S3C2410+IDT7204 structure were used, on the software real-time operating system uC/OS-II were used in the design of embedded virtual oscilloscope. ARM9 microprocessor's high speed handling ability are fully used, as well as FIFO in the read-write control logic, the superiority in high speed data exchange aspect, realizes the double channel synchronization profile demonstration. the multi-task run and the real-time processing were realized by using on the uC/OS-II operating system's in ARM9 microprocessor transplant. This oscilloscope has the cost lowly, to be possible to as the common oscilloscope, also to be possible to as an intelligent module the merit which used in the embedded system.

Design and Realization Real-time Edge Detection System Based on DM642

2011 ◽  
Vol 216 ◽  
pp. 233-237
Author(s):  
W.H. Xiao ◽  
X. Wan ◽  
Z.M. Zhang ◽  
R. Liu ◽  
X.Y. Lu
Keyword(s):  
Edge Detection ◽  
Real Time ◽  
Detection System ◽  
Image Acquisition ◽  
Processing System ◽  
Video Image ◽  
Ministry Of Education ◽  
Embedded Processor ◽  
Real Time Processing ◽  
Video Decoder

This paper introduces the design of a DSP-based video image acquisition and real-time processing system. In this paper, as the main embedded processor TMS320DM642 build real-time edge detection hardware platform. TVP5150PBS video decoder is adopted to acquire video signal and data stream ,and CPLD device is configured for system logic Control, achieve real-time video image acquisition and processing. Experiments show that the system can effectively carry out edge detection, to meet the real-time. The research is supported by the Key Laboratory of Nondestructive Test Ministry of Education. The author appreciates the state natural science fund(60577016), Aero-Science fund (2009ZD56008) and province fund (2009GZW00251).

Pattern Recognition Application of Improved SURF Algorithm in Mobile Phone

2014 ◽  
Vol 610 ◽  
pp. 471-476 ◽  
Author(s):  
Hui Bai Wang ◽  
Lu Nan Yang
Keyword(s):  
Pattern Recognition ◽  
Mobile Phone ◽  
Real Time ◽  
Mobile Applications ◽  
Theory And Practice ◽  
Feature Points ◽  
Real Time Processing ◽  
Time Processing ◽  
Speeded Up Robust Features ◽  
Video Frames

Directed at the defects of time-consuming feature points extracting and out-of-sync between matching feature points and processing video frames in the original SURF (Speeded Up Robust Features) algorithm in mobile pattern recognition applications. For these shortcomings, this paper proposes an improved SURF algorithm. The algorithm uses buffer mechanism. An adaptation threshold is used when extracting feature points. Experimental results show that using the improved SURF algorithm in mobile applications has achieved the purpose of real-time processing. It has certain values in both theory and practice.

scholarly journals Implementation of Thermal Event Image Processing Algorithms on NVIDIA Tegra Jetson TX2 Embedded System-on-a-Chip

Energies ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4416
Author(s):  
Bartłomiej Jabłoński ◽  
Dariusz Makowski ◽  
Piotr Perek
Keyword(s):  
Image Processing ◽  
Embedded System ◽  
Real Time ◽  
Plasma Diagnostics ◽  
Nuclear Fusion ◽  
Real Time Processing ◽  
Time Processing ◽  
Processing Algorithms ◽  
System On A Chip ◽  
Events Detection

Advances in Infrared (IR) cameras, as well as hardware computational capabilities, contributed towards qualifying vision systems as reliable plasma diagnostics for nuclear fusion experiments. Robust autonomous machine protection and plasma control during operation require real-time processing that might be facilitated by Graphics Processing Units (GPUs). One of the current aims of image plasma diagnostics involves thermal events detection and analysis with thermal imaging. The paper investigates the suitability of the NVIDIA Jetson TX2 Tegra-based embedded platform for real-time thermal events detection. Development of real-time processing algorithms on an embedded System-on-a-Chip (SoC) requires additional effort due to the constrained resources, yet low-power consumption enables embedded GPUs to be applied in MicroTCA.4 computing architecture that is prevalent in nuclear fusion projects. For this purpose, the authors have proposed, developed and optimised GPU-accelerated algorithms with the use of available software tools for NVIDIA Tegra systems. Furthermore, the implemented algorithms are evaluated and benchmarked on Wendelstein 7-X (W7-X) stellarator experimental data against the corresponding alternative Central Processing Unit (CPU) implementations. Considerable improvement is observed for the accelerated algorithms that enable real-time detection on the embedded SoC platform, yet some encountered limitations when developing parallel image processing routines are described and signified.

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