High Real-Time Design of Digital Pulse Compression Based on FPGA
2015 ◽
Vol 2015
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pp. 1-7
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Keyword(s):
Because of the poor real-time performance of in-place fast Fourier transforms, a reconfigurable radix-4 FFT processor is studied and designed, which is based on decimation-in-time and single floating-point computation. The proposed method adopts “pipeline and parallel” structure for accessing multiple memories to improve the FFT processing speed, and then it is applied to digital pulse compression. The experimental result shows that the proposed FFT based on radix-4 computation can implement digital pulse compression rapidly under no adding hardware resources. The proposed method can be also applied to other radix FFTs.
2013 ◽
Vol 765-767
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pp. 2021-2025
2014 ◽
Vol 620
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pp. 228-232
2021 ◽
Vol 2021
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pp. 1-8
Keyword(s):
2014 ◽
Vol 7
(4)
◽
pp. 694
Keyword(s):
2014 ◽
Vol 39
(5)
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pp. 658-663
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Simulation research on real-time performance of CAN bus based on distributed dynamic prior-ity queue
2011 ◽
Vol 25
(7)
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pp. 591-596
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