scholarly journals A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Antony Savich ◽  
Shawki Areibi
Keyword(s):  
Low Power ◽  
High Performance ◽  
Matrix Multiplication ◽  
Hardware Accelerator ◽  
Power Performance ◽  
Matrix Operations ◽  
Simulated System ◽  
Scalable Hardware ◽  
Functional Prototype ◽  
High Performance Computation

Many applications ranging from machine learning, image processing, and machine vision to optimization utilize matrix multiplication as a fundamental block. Matrix operations play an important role in determining the performance of such applications. This paper proposes a novel efficient, highly scalable hardware accelerator that is of equivalent performance to a 2 GHz quad core PC but can be used in low-power applications targeting embedded systems requiring high performance computation. Power, performance, and resource consumption are demonstrated on a fully-functional prototype. The proposed hardware accelerator is 36× more energy efficient per unit of computation compared to state-of-the-art Xeon processor of equal vintage and is 14× more efficient as a stand-alone platform with equivalent performance. An important comparison between simulated system estimates and real system performance is carried out.

scholarly journals Programming the Adapteva Epiphany 64-core network-on-chip coprocessor

2015 ◽  
Vol 31 (4) ◽  
pp. 285-302 ◽  
Author(s):  
Anish Varghese ◽  
Bob Edwards ◽  
Gaurav Mitra ◽  
Alistair P Rendell
Keyword(s):  
Low Power ◽  
High Performance Computing ◽  
High Performance ◽  
Large Scale ◽  
Matrix Multiplication ◽  
Building Blocks ◽  
Mesh Network ◽  
Peak Performance ◽  
Core Network ◽  
Performance Computing

Energy efficiency is the primary impediment in the path to exascale computing. Consequently, the high-performance computing community is increasingly interested in low-power high-performance embedded systems as building blocks for large-scale high-performance systems. The Adapteva Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of theoretical performance. However, with just 32 KB of memory per eCore for storing both data and code, programming the Epiphany system presents significant challenges. In this paper we evaluate the performance of a 64-core Epiphany system with a variety of basic compute and communication micro-benchmarks. Further, we implemented two well known application kernels, 5-point star-shaped heat stencil with a peak performance of 65.2 GFLOPS and matrix multiplication with 65.3 GFLOPS in single precision across 64 Epiphany cores. We discuss strategies for implementing high-performance computing application kernels on such memory constrained low-power devices and compare the Epiphany with competing low-power systems. With future Epiphany revisions expected to house thousands of cores on a single chip, understanding the merits of such an architecture is of prime importance to the exascale initiative.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

High-Performance and Low-Power Full Color Reflective LCD for New Applications

2019 ◽  
pp. 1411
Author(s):  
Hiroyuki Hakoi ◽  
Ming Ni ◽  
Junichi Hashimoto ◽  
Takashi Sato ◽  
Shinji Shimada ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Color ◽  
New Applications

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals Optimization of a Low-Power Chemoresistive Gas Sensor: Predictive Thermal Modelling and Mechanical Failure Analysis

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 783 ◽  
Author(s):  
Andrea Gaiardo ◽  
David Novel ◽  
Elia Scattolo ◽  
Michele Crivellari ◽  
Antonino Picciotto ◽  
...  
Keyword(s):  
Low Power ◽  
Failure Analysis ◽  
Gas Sensors ◽  
High Performance ◽  
Gas Sensing ◽  
Mechanical Failure ◽  
Sensing Applications ◽  
Theoretical Approaches ◽  
Sensing Material ◽  
Silicon Bulk

The substrate plays a key role in chemoresistive gas sensors. It acts as mechanical support for the sensing material, hosts the heating element and, also, aids the sensing material in signal transduction. In recent years, a significant improvement in the substrate production process has been achieved, thanks to the advances in micro- and nanofabrication for micro-electro-mechanical system (MEMS) technologies. In addition, the use of innovative materials and smaller low-power consumption silicon microheaters led to the development of high-performance gas sensors. Various heater layouts were investigated to optimize the temperature distribution on the membrane, and a suspended membrane configuration was exploited to avoid heat loss by conduction through the silicon bulk. However, there is a lack of comprehensive studies focused on predictive models for the optimization of the thermal and mechanical properties of a microheater. In this work, three microheater layouts in three membrane sizes were developed using the microfabrication process. The performance of these devices was evaluated to predict their thermal and mechanical behaviors by using both experimental and theoretical approaches. Finally, a statistical method was employed to cross-correlate the thermal predictive model and the mechanical failure analysis, aiming at microheater design optimization for gas-sensing applications.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods

2021 ◽  
Vol 32 (8) ◽  
pp. 2035-2048
Author(s):  
Mochamad Asri ◽  
Dhairya Malhotra ◽  
Jiajun Wang ◽  
George Biros ◽  
Lizy K. John ◽  
...  
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
Hardware Accelerator ◽  
Performance Computing
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