scholarly journals Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Jubayer Jalil ◽  
Mamun Bin Ibne Reaz ◽  
Mohammad Arif Sobhan Bhuiyan ◽  
Labonnah Farzana Rahman ◽  
Tae Gyu Chang
Keyword(s):  
Phase Noise ◽  
Radio Frequency Identification ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Phase Locked Loops ◽  
Cmos Process ◽  
Voltage Controlled Oscillators ◽  
Delay Cell ◽  
Frequency Identification ◽  
Low Phase Noise

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

2012 ◽  
Vol 33 (7) ◽  
pp. 075004 ◽  
Author(s):  
Haijun Gao ◽  
Lingling Sun ◽  
Xiaofei Kuang ◽  
Liheng Lou
Keyword(s):  
Phase Noise ◽  
Fine Tuning ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Low Phase Noise

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals Low Phase Noise Current Starved Ring VCO on MOS Capacitance

2019 ◽  
Vol 8 (10) ◽  
pp. 4569-4574
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Control Voltage ◽  
Wireless System ◽  
Noise Current ◽  
And Control ◽  
Low Phase Noise

In Wireless communication system VCO is major part which regulates the frequency according to the voltage. Ring oscillator of one type of VCO is used. The topology of Ring oscillator is current starved Ring VCO, is used. In this topology the oscillation frequency is regulated by MOS capacitance. MOS capacitance is added at the end of every stage of inverter.180 nm CMOS technology is used in this paper. The supply voltage is 1.8V and control voltage is varied from 0V to 1.8V. The simulated results are shown that good tuning range from 2.06GHz to 2.62 GHz. which is used in application of wireless system. The phase noise is measured -112dbc/Hz at 1MHz.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

Development of Varied CMOS Ring Oscillator Topologies in 0.13-μm CMOS Technology

2013 ◽  
Vol 446-447 ◽  
pp. 882-886
Author(s):  
Sohiful Anuar Zainol Murad ◽  
Rizalafande Che Ismail ◽  
Mohamad Shahimin Mukhzeer ◽  
Ahmad Mohd Fairus ◽  
Sapawi Rohana
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Variable Resistor ◽  
Wireless Applications ◽  
Differential Ring ◽  
Delay Cell ◽  
Simulation Results ◽  
Offset Frequency

This paper presents varied CMOS ring oscillator topologies using Silterra 0.13-µm Process. Three topologies of ring oscillators have been designed which is the single-ended ring oscillator, differential ring oscillator and ring oscillator based variable resistor for 2.4 GHz wireless applications. The proposed designs consist of five stages delay cell. The simulation results show that a single-ended ring oscillator obtained the lowest power consumption of 0.41 mW, while differential oscillator achieves phase noise of −64.44 dBc/Hz at 1 MHz offset frequency. However, ring oscillator based variable resistor did not achieve any significant improvement. The proposed design is oscillates at 2.4 GHz.

Ring Oscillator Phase Noise Properties due to PSN with Deterministic Frequency

2012 ◽  
Vol 496 ◽  
pp. 527-533
Author(s):  
Na Bai ◽  
Hong Gang Zhou ◽  
Qiu Lei Wu ◽  
Chun Yu Peng
Keyword(s):  
Phase Noise ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Analysis Method ◽  
Noise Performance ◽  
Supply Noise ◽  
Total Phase ◽  
Phase Noise Performance ◽  
Oscillator Phase Noise ◽  
Oscillator Phase

In this paper, ring oscillator phase noise caused by power supply noise (PSN) with deterministic frequency is analyzed. Results show that phase noise caused by deterministic noise is only an impulse series. Compared with the jitter caused by PSN, the phase noise caused by PSN with deterministic frequency contributes considerably less to total phase noise performance. To verify the analysis method, a CMOS ring oscillator is designed and fabricated using SMIC 0.13 µm CMOS process. Comparisons between the analytical results and measurements prove the accuracy of the proposed method

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