scholarly journals Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-7
Author(s):  
Sahar Arshad ◽  
Muhammad Ismail ◽  
Usman Ahmad ◽  
Anees ul Husnain ◽  
Qaiser Ijaz
Keyword(s):  
Frequency Synthesizer ◽  
Switching Time ◽  
Optimized Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Pll Frequency Synthesizer ◽  
Significant Performance ◽  
Simulation Results ◽  
Effective Design

We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial application, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire significant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization is contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated by the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design.

scholarly journals Optimization of frequency settling time of PLL using 3rd MASH Sigma Delta Modulator

2020 ◽  
Vol 9 (3) ◽  
pp. 2853-2859
Keyword(s):  
Frequency Synthesizer ◽  
Settling Time ◽  
Design System ◽  
Type Ii ◽  
Transient Responses ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Pll Frequency Synthesizer ◽  
Simulation Results ◽  
Improved Performance

To reduce settling time of PLL, an attempt to optimize the parameters has been proposed in this paper. The transient responses of various Phase Locked Loop (PLL) frequency synthesizer have been comparied with their active and passive poles effect. These results are presented on a type-II 3rd order PLL frequency synthesizer employing a 3rd order MASH sigma delta modulator. The simulation results show the improved performance of the fractional frequency synthesizer for the communication system. These results have been simulated using Advanced Design System(ADS) tool.

DESIGNING LOW POWER OF SIGMA DELTA MODULATOR FOR BIOMEDICAL APPLICATION

2005 ◽  
Vol 17 (04) ◽  
pp. 181-185 ◽  
Author(s):  
HO-YIN LEE ◽  
CHEN-MING HSU ◽  
SHENG-CHIA HUANG ◽  
YI-WEI SHIH ◽  
CHING-HSING LUO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Loop Filter ◽  
Biomedical Signal ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Power Application

This paper discusses the design of micro power Sigma-delta modulator with oversampling technology. This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electro-cardiogram (ECG), Electroencephalogram (EEG) etc. [1]. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system. The original biomedical signal can be reconstructed by simply applying the digital bit stream from the modulator output through a low-pass filter. The loop filter of this modulator has been implemented by using switch capacitor (SC) integrators and using simple circuitry consists of OpAmps, Comparator and DAC. In general, the resolution of modulator is about 10 bits for biomedical application. In this two order Sigma-delta modulator simulation results of the 1.8V sigma delta modulator show a 68 dB signal-to-noise-and-distortion ratio (SNDR) in 4 kHz biomedical signal bandwidth and a sampling frequency equal to 1 MHz in the 0.18 μ m CMOS technology. The power consumption is 400 μ W. It is very suitable for low power application of biomedical instrument design.

AN EFFICIENT LOW-POWER SIGMA-DELTA MODULATOR FOR MULTI-STANDARD WIRELESS APPLICATIONS

2012 ◽  
Vol 21 (04) ◽  
pp. 1250028 ◽  
Author(s):  
B. HODA SEYEDHOSSEINZADEH ◽  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Cmos Technology ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Wireless Applications ◽  
Design And Implementation ◽  
Simulation Results ◽  
System Level Simulations

This paper describes the design and implementation of a reconfigurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5 MHz, 10 MHz, 1.92 MHz, 0.5 MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5 mW using a single 1 V power supply.

The Design of the Integrator of Sigma-Delta Modulator

2013 ◽  
Vol 562-565 ◽  
pp. 477-481
Author(s):  
Xiao Wei Liu ◽  
Song Chen ◽  
Liang Liu ◽  
Jian Yang ◽  
Wei Ping Chen
Keyword(s):  
Low Frequency ◽  
Clock Signal ◽  
Gain Bandwidth ◽  
Two Phase ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Fully Differential ◽  
Unity Gain ◽  
Simulation Results ◽  
Sigma Delta Adc

A kind of fully differential integrator is designed for the modulator of Sigma-delta ADC in this paper. Fully differential structure is adopted to enlarge the amplitude of output, restrain nonlinearity and increase competence of anti-interference. The frequency of signal in this design is 10kHz and the frequency of clock signal is 100kHz. The design of fully differential integrator, capacitive common mode feedback, two-phase unoverlapping clock and switched capacitor integrator are accomplished in this paper. The simulation results in Cadence using 0.5um process show that the low-frequency gain of operational amplifier is 69.87dB, unity gain bandwidth is 37.74MHz, phase margin is 67.73 degrees and slew rate is more than 31V/μs.

Analysis of Harmonic Distortion of Sigma-Delta Modulator

2015 ◽  
Vol 645-646 ◽  
pp. 980-985
Author(s):  
Dong Yan ◽  
Wen Ning Jiang ◽  
Si Qi Tao ◽  
Jian Yang ◽  
Liang Yin ◽  
...  
Keyword(s):  
High Performance ◽  
Harmonic Distortion ◽  
Differential Topology ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Noise Floor ◽  
Fully Differential ◽  
Non Linear ◽  
Even Order ◽  
Simulation Results

In this paper, the harmonic distortion of fourth-order sigma-delta modulator is analyzed. Based on the analysis non-ideal models are established and simulation results demonstrated the validity of these models. The non-linear capacitors introduce harmonic distortion and the non-linear on-resistance nearly only introduce second order harmonic distortion. The non-ideal integrators can increase the noise floor of the modulator.The fully-differential topology can be adopted to eliminate even order harmonic distortion and the operational amplifier with high performance can also be used to decrease noise floor of the modulator.

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

2013 ◽  
Vol 660 ◽  
pp. 113-118
Author(s):  
Jhin Fang Huang ◽  
Wen Cheng Lai ◽  
Kun Jie Huang ◽  
Ron Yi Liu
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area ◽  
Low Pass ◽  
Σδ Modulator

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

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