scholarly journals Nanosensor Data Processor in Quantum-Dot Cellular Automata

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Fenghui Yao ◽  
Mohamed Saleh Zein-Sabatto ◽  
Guifeng Shao ◽  
Mohammad Bodruzzaman ◽  
Mohan Malkani
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Input Data ◽  
Cmos Technology ◽  
Sigmoid Function ◽  
Lower Power ◽  
Quantum Dot Cellular Automata ◽  
Data Processor ◽  
High Level

Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates, and (iii) generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.

Design of First Adder/Subtractor Using Quantum-Dot Cellular Automata

2011 ◽  
Vol 403-408 ◽  
pp. 3392-3397 ◽  
Author(s):  
Ali Shahidinejad ◽  
Ali Selamat
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Lower Power ◽  
Quantum Dot Cellular Automata

Quantum-dot cellular automata (QCA) is an emerging nanotechnology that provides faster speed, smaller size and lower power consumption compared to the current transistor-based technology. Adder/ subtractor is a useful component for the design of many computation systems and functional circuits. This paper proposes a practical XOR design in QCA. Then the first adder/subtractor circuit in QCA is designed and simulated using the proposed XOR design. Results of simulation were carried out using QCADesigner.

scholarly journals Design of Efficient Full Adder in Quantum-Dot Cellular Automata

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Design ◽  
Majority Gate ◽  
Feature Size ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

A Novel Quantum-Dot Cellular Automata XOR Design

2012 ◽  
Vol 622-623 ◽  
pp. 545-550 ◽  
Author(s):  
Ali Shahidinejad ◽  
Ali Farrokhtala ◽  
Saman Asadi ◽  
Maryam Mofarrahi ◽  
Toni Anwar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Input Frequency ◽  
High Input ◽  
Lower Power ◽  
Quantum Dot Cellular Automata ◽  
Comparison Of Results ◽  
Traditional Approaches

Quantum-dot cellular automata (QCA) is an emerging nanotechnology that promises faster speed, smaller size, and lower power consumption compared to the transistor-based technology. Moreover, XOR is a useful component for the design of many logical and functional circuits. This paper proposes a novel and efficient QCA XOR design. The proposed XOR design has been compared to a few recent designs in terms of area, speed and complexity. Comparison of results illustrates significant improvements in our design as compared to traditional approaches. Also simulation proves that the proposed XOR design is completely robust and more sustainable to high input frequency as compared to other designs. This robustness is highly significant when this component is applied for realizing larger designs.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

scholarly journals Editorial for the Special Issue on “Quantum-Dot Cellular Automata (QCA) and Low Power Application”

2018 ◽  
Vol 8 (4) ◽  
pp. 40
Author(s):  
Stefania Perri
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Consumption ◽  
Low Power ◽  
Special Issue ◽  
Innovative Technologies ◽  
Quantum Dot Cellular Automata ◽  
Power Application

Challenges created by the trend of increasingly reducing the size of transistors have made necessary innovative technologies to limit undesirable impacts on the performance speed and power consumption of future designs. [...]

scholarly journals Optimum multiplexer design in quantum-dot cellular automata

2020 ◽  
Vol 17 (1) ◽  
pp. 148 ◽  
Author(s):  
Esam AlKaldy ◽  
Ali H Majeed ◽  
Mohd Shamian Zainal ◽  
Danial MD Nor
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Boolean Function ◽  
High Speed ◽  
Building Blocks ◽  
Cmos Technology ◽  
Quantum Dot Cellular Automata ◽  
Quantum Technology ◽  
Logical Functions ◽  
Novel Design

<p>Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.</p>

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing

2020 ◽  
Vol 18 (06) ◽  
pp. 2050032
Author(s):  
Suhaib Ahmed ◽  
Syed Farah Naz
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Communication Networks ◽  
Data Transfer ◽  
Fault Tolerant ◽  
Satellite Communications ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

The issues faced by Complementary metal oxide semi-conductor (CMOS) technology in the nanoregime have led to the research of other possible technologies which can operate with same functionalities however, with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). At present, logic circuit designs using QCA have been comprehensively researched and one such application area being investigated is data transmission. Various data transfer techniques for reliable data transfer are available and among them convolution coding is being widely used in mobile, radio and satellite communications. Considering the evolution towards nano communication networks, in this paper an ultra-proficient designs of 1/2 rate and 1/3 rate convolution encoders based on a cost-efficient and fault tolerant XOR gate design have been proposed for application in nano communication networks. Based on the performance analysis, it is observed that the proposed designs are efficient in respect to cell count, area, delay and circuit cost and achieves performance improvement up to 40.21% for 1/2 encoder and 31.81% for 1/3 encoder compared to the best design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. The proposed designs can thus be efficiently utilized in various nanocommunication applications requiring minimal area and ultra-low power consumption.

Sign in / Sign up

Export Citation Format

Share Document