scholarly journals Continuous-TimeΣΔADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Amira Abbes ◽  
Mohieddine Amor Benammar
Keyword(s):  
Power Consumption ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Clock Frequency ◽  
Pixel Resolution ◽  
Loop Filter ◽  
Sigma Delta ◽  
Variable Gain

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

DESIGNING LOW POWER OF SIGMA DELTA MODULATOR FOR BIOMEDICAL APPLICATION

2005 ◽  
Vol 17 (04) ◽  
pp. 181-185 ◽  
Author(s):  
HO-YIN LEE ◽  
CHEN-MING HSU ◽  
SHENG-CHIA HUANG ◽  
YI-WEI SHIH ◽  
CHING-HSING LUO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Loop Filter ◽  
Biomedical Signal ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Power Application

This paper discusses the design of micro power Sigma-delta modulator with oversampling technology. This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electro-cardiogram (ECG), Electroencephalogram (EEG) etc. [1]. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system. The original biomedical signal can be reconstructed by simply applying the digital bit stream from the modulator output through a low-pass filter. The loop filter of this modulator has been implemented by using switch capacitor (SC) integrators and using simple circuitry consists of OpAmps, Comparator and DAC. In general, the resolution of modulator is about 10 bits for biomedical application. In this two order Sigma-delta modulator simulation results of the 1.8V sigma delta modulator show a 68 dB signal-to-noise-and-distortion ratio (SNDR) in 4 kHz biomedical signal bandwidth and a sampling frequency equal to 1 MHz in the 0.18 μ m CMOS technology. The power consumption is 400 μ W. It is very suitable for low power application of biomedical instrument design.

scholarly journals A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO

2018 ◽  
Vol 2018 ◽  
pp. 1-8
Author(s):  
Lei Ma ◽  
Na Yan ◽  
Sizheng Chen ◽  
Yangzi Liu ◽  
Hao Min
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Frequency Resolution ◽  
Corner Frequency ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Class C ◽  
Digitally Controlled Oscillator

This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the 1/f3 corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.

scholarly journals [Paper] A 20Mfps Global Shutter CMOS Image Sensor with Improved Light Sensitivity and Power Consumption Performances

2016 ◽  
Vol 4 (2) ◽  
pp. 149-154 ◽  
Author(s):  
Rihito Kuroda ◽  
Yasuhisa Tochigi ◽  
Ken Miyauchi ◽  
Tohru Takeda ◽  
Hidetake Sugo ◽  
...  
Keyword(s):  
Power Consumption ◽  
Cmos Image Sensor ◽  
Light Sensitivity ◽  
Image Sensor

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

A CMOS Image Sensor with a Novel Passive Pixel Array and High Precision Current Amplifier for a Compact Digital X-ray Detector

2020 ◽  
Vol 10 (11) ◽  
pp. 2745-2753
Author(s):  
Jimin Cheon ◽  
Dongmyung Lee ◽  
Hojong Choi
Keyword(s):  
High Precision ◽  
Dynamic Range ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Total Power ◽  
Cmos Process ◽  
Current Amplifier ◽  
X Ray ◽  
Total Power Consumption ◽  
Pixel Array

An active pixel sensor (APS) in a digital X-ray detector is the dominant circuitry for a CMOS image sensor (CIS) despite its lower fill factor (FF) compared to that of a passive pixel sensor (PPS). Although the PPS provides higher FF, its overall signal-to-noise ratio (SNR) is lower than that of the APS. The required high resolution and small focal plane can be achieved by reducing the number of transistors and contacts per pixel. We proposed a novel passive pixel array and a high precision current amplifier to improve the dynamic range (DR) without minimizing the sensitivity for diagnostic compact digital X-ray detector applications. The PPS can be an alternative to improve the FF. However, size reduction of the feedback capacitor causes degradation of SNR performance. This paper proposes a novel PPS based on readout and amplification circuits with a high precision current amplifier to minimize performance degradation. The expected result was attained with a 0.35-μm CMOS process parameter with power supply voltage of 3.3 V. The proposed PPS has a saturation signal of 1.5 V, dynamic range of 63.5 dB, and total power consumption of 13.47 mW. Therefore, the proposed PPS readout circuit improves the dynamic range without sacrificing the sensitivity.

An Energy-Efficient Receiver for Human Body Communication

2012 ◽  
Vol 195-196 ◽  
pp. 84-89
Author(s):  
Da Hui Zhang ◽  
Ze Dong Nie ◽  
Feng Guan ◽  
Lei Wang
Keyword(s):  
Low Power ◽  
Human Body ◽  
Data Transmission ◽  
Energy Efficient ◽  
Low Noise ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Variable Gain ◽  
Active Balun ◽  
Noise Amplifier

A low-power, wideband signaling receiver for data transmission through a human body was presented in this paper. The receiver utilized a novel implementation of energy-efficient wideband impulse communication that uses the human body as the transmission medium, provides low power consumption, high reception sensitivity. The receiver consists of a low-noise amplifier, active balun, variable gain amplifier (VGA) Gm-C filter, comparator, and FSK demodulator. It was designed with 0.18um CMOS process in an active area of 1.54mm0.414mm. Post-simulation showed that the receiver has a gain range of-2dB~40dB. The receiver consumes 4mW at 1.8V supply and achieves transmission bit energy of 0.8nJ/bit.

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