scholarly journals Design a Bioamplifier with High CMRR

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Yu-Ming Hsiao ◽  
Miin-Shyue Shiau ◽  
Kuen-Han Li ◽  
Jing-Jhong Hou ◽  
Heng-Shou Hsu ◽  
...  
Keyword(s):  
Biomedical Applications ◽  
Process Variations ◽  
Cmos Technology ◽  
Rejection Ratio ◽  
Self Bias ◽  
High Cmrr ◽  
Three Stages ◽  
Low Offset ◽  
Cmos Amplifier ◽  
Very High

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 μm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 μV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations. This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.

scholarly journals A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

2018 ◽  
Vol 2 (2) ◽  
Author(s):  
Soma Ahmadi ◽  
Seyed Javad Azhari
Keyword(s):  
Second Generation ◽  
Current Mode ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Instrumentation Amplifier ◽  
Intrinsic Resistance ◽  
Common Mode ◽  
Fully Differential ◽  
High Cmrr ◽  
Very High

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW.  Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits.

CMOS-MEMS Based Current Mirror MOSFET Embedded Pressure Sensor for Healthcare and Biomedical Applications

2013 ◽  
Vol 647 ◽  
pp. 315-320 ◽  
Author(s):  
Pradeep Kumar Rathore ◽  
Brishbhan Singh Panwar
Keyword(s):  
Pressure Sensor ◽  
Biomedical Applications ◽  
Circuit Simulation ◽  
Applied Pressure ◽  
Pressure Sensors ◽  
Cmos Technology ◽  
Current Mirror ◽  
Sensing Element ◽  
Pressure Sensing ◽  
Cmos Mems

This paper reports on the design and optimization of current mirror MOSFET embedded pressure sensor. A current mirror circuit with an output current of 1 mA integrated with a pressure sensing n-channel MOSFET has been designed using standard 5 µm CMOS technology. The channel region of the pressure sensing MOSFET forms the flexible diaphragm as well as the strain sensing element. The piezoresistive effect in MOSFET has been exploited for the calculation of strain induced carrier mobility variation. The output transistor of the current mirror forms the active pressure sensing MOSFET which produces a change in its drain current as a result of altered channel mobility under externally applied pressure. COMSOL Multiphysics is utilized for the simulation of pressure sensing structure and Tspice is employed to evaluate the characteristics of the current mirror pressure sensing circuit. Simulation results show that the pressure sensor has a sensitivity of 10.01 mV/MPa. The sensing structure has been optimized through simulation for enhancing the sensor sensitivity to 276.65 mV/MPa. These CMOS-MEMS based pressure sensors integrated with signal processing circuitry on the same chip can be used for healthcare and biomedical applications.

Application of the MCDA method for assessing new technologies for familial hypercholesterolaemia treatment

2021 ◽  
Vol 13 (1) ◽  
pp. 14-20
Author(s):  
Marisa Santos ◽  
◽  
Quenia Morais ◽  
Helena Cramer ◽  
Marcelo Assad ◽  
...  
Keyword(s):  
New Technologies ◽  
Familial Hypercholesterolaemia ◽  
Low Density Lipoprotein ◽  
Density Lipoprotein ◽  
Cardiovascular Death ◽  
Hereditary Disease ◽  
New Drugs ◽  
Three Stages ◽  
Indirect Comparisons ◽  
Very High

Objective: Familial hypercholesterolaemia is a hereditary disease characterized by very high levels of low-density lipoprotein cholesterol and an elevated risk of early-onset cardiovascular disorders. New drugs provide alternatives for the treatment of patients with homozygous familial hypercholesterolaemia. The study aims to explore a practical application of multiple-criteria decision analysis on prioritization of new and emerging technologies for familial hypercholesterolaemia. Methods: The decision model was constructed using the MACBETH method. There were three stages: structuring the problem, measuring the performance of alternatives, and building the model. The weights for alternatives and levels were obtained by indirect comparisons, which evaluated the attractiveness of the performance levels of the criteria using the swing weights technique. Results: The drugs lomitapide, ezetimibe, evolocumab, and mipomersen were selected as alternatives for decision-making. “Cardiovascular Death”, “Stroke” and “Acute Myocardial Infarction” had the three most significant weights. The criteria with the lowest weights were “Comfort” and “LDL-C Reduction”. The top-ranked technology was evolocumab, with an overall score of 59.87, followed by ezetimibe, with a score of 37.21. Conclusion: How to apply the result of a higher score in the actual decisionmaking process still requires further studies. The case in question showed that evolocumab has more performance benefits than other drugs but with a cost approximately 50 times higher

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

2021 ◽  
Author(s):  
Chaudhry Indra Kumar
Keyword(s):  
Energy Transfer ◽  
Energy Efficient ◽  
Linear Energy Transfer ◽  
Mixed Mode ◽  
Biomedical Applications ◽  
Soft Errors ◽  
Cmos Technology ◽  
Radiation Hardness ◽  
Memory Element ◽  
Low Area

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

2022 ◽  
Vol 17 (01) ◽  
pp. C01040
Author(s):  
C. Zhao ◽  
D. Guo ◽  
Q. Chen ◽  
N. Fang ◽  
Y. Gan ◽  
...  
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Test Results ◽  
Eye Diagram ◽  
Optical Links ◽  
Optical Module ◽  
Active Feedback ◽  
High Bandwidth ◽  
Output Driver ◽  
Very High

Abstract This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

scholarly journals A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

2017 ◽  
Vol 2017 ◽  
pp. 1-10
Author(s):  
Jinpeng Qiu ◽  
Tong Liu ◽  
Xubin Chen ◽  
Yongheng Shang ◽  
Jiongjiong Mo ◽  
...  
Keyword(s):  
Operational Amplifier ◽  
Supply Voltage ◽  
Bandgap Reference ◽  
Digital To Analog Converter ◽  
Future Design ◽  
Differential Nonlinearity ◽  
Self Bias ◽  
Analog Converter ◽  
Digital To Analog ◽  
Low Offset

This paper presents a new 12-bit digital to analog converter (DAC) circuit based on a low-offset bandgap reference (BGR) circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL) of the output voltages is less than 0.45 LSB and integral nonlinearity (INL) less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

A CMOS Automatic Gain Control Circuit for Biomedical Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1308-1313
Author(s):  
Zhi Qiang Gao ◽  
Fu Xiang Huang ◽  
Jing Li ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Exponential Function ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Cmos Technology ◽  
Chip Area ◽  
Gain Variation ◽  
Linearity Error

In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.

Fully Differential Class-AB OTA with Improved CMRR

2017 ◽  
Vol 26 (11) ◽  
pp. 1750169 ◽  
Author(s):  
Francesco Centurelli ◽  
Pietro Monsurrò ◽  
Gaetano Parisi ◽  
Pasquale Tommasino ◽  
Alessandro Trifiletti
Keyword(s):  
Cmos Technology ◽  
Current Mirror ◽  
Differential Mode ◽  
Common Mode ◽  
Common Mode Rejection Ratio ◽  
Class Ab ◽  
Fully Differential ◽  
Rejection Ratio ◽  
Mode Behavior ◽  
The Common

This paper presents a fully differential class-AB current mirror OTA that improves the common-mode behavior of a topology that presents very good differential-mode performance but poor common-mode rejection ratio (CMRR). The proposed solution requires a low-current auxiliary circuit driven by the input signal, to compensate the effect of the common-mode input component. Simulations in 40-nm CMOS technology show a net reduction of common-mode gain of more than 90[Formula: see text]dB without affecting the differential-mode behavior; a sample-and-hold amplifier exploiting the proposed amplifier has also been simulated.

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