scholarly journals A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Joshua S. Monson ◽  
Mike Wirthlin ◽  
Brad Hutchings
Keyword(s):  
Fault Injection ◽  
Hard Core ◽  
Programmable Logic ◽  
Single Event ◽  
Test Bed ◽  
Access Port ◽  
Single Event Upsets ◽  
Embedded Platform ◽  
Internal Configuration ◽  
Bit Stream

An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the “hard core” PowerPC, running the Linux OS and several peripherals implemented in “soft” (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that the Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is mapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within the system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller.

scholarly journals Tracing Fault Effects in FPGA Systems

2014 ◽  
Vol 60 (1) ◽  
pp. 92-97 ◽  
Author(s):  
Mariusz Węgrzyn ◽  
Janusz Sosnowski
Keyword(s):  
Detailed Analysis ◽  
Fault Injection ◽  
Original Method ◽  
Injection Technique ◽  
Transient Faults ◽  
Single Event ◽  
Single Event Upsets ◽  
Fault Handling

Abstract The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets - SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.

scholarly journals VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 899
Author(s):  
Bushra Sultana ◽  
Anees Ullah ◽  
Arsalan Ali Malik ◽  
Ali Zahir ◽  
Pedro Reviriego ◽  
...  
Keyword(s):  
State Of The Art ◽  
Fold Increase ◽  
Programmable Logic ◽  
Single Chip ◽  
Access Port ◽  
Fine Grain ◽  
Art Works ◽  
Run Time ◽  
Internal Configuration ◽  
Run Time Reconfiguration

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

2014 ◽  
Vol 23 (06) ◽  
pp. 1450081 ◽  
Author(s):  
REZA OMIDI GOSHEBLAGH ◽  
KARIM MOHAMMADI
Keyword(s):  
Field Programmable Gate Array ◽  
Fault Injection ◽  
Soft Error ◽  
Space Systems ◽  
Single Event ◽  
Single Event Upsets ◽  
Average Area ◽  
Error Mitigation ◽  
Field Programmable ◽  
Mitigation Techniques

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

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