scholarly journals HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture

2012 ◽  
Vol 2012 ◽  
pp. 1-17 ◽  
Author(s):  
Alexander Thomas ◽  
Michael Rückauer ◽  
Jürgen Becker
Keyword(s):  
Power Consumption ◽  
Reconfigurable Computing ◽  
Register Transfer Level ◽  
Coarse Grained ◽  
Fine Grained ◽  
Reconfigurable Devices ◽  
Resource Requirements ◽  
Broad Variety ◽  
And Performance ◽  
Reconfigurable Hardware Architecture

Since the introduction of the first reconfigurable devices in 1985 the field of reconfigurable computing developed a broad variety of architectures from fine-grained to coarse-grained types. However, the main disadvantages of the reconfigurable approaches, the costs in area, and power consumption, are still present. This contribution presents a solution for application-driven adaptation of our reconfigurable architecture at register transfer level (RTL) to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. Furthermore, implemented runtime adaptive features like online routing and configuration sequencing will be presented and discussed. A presentation of the prototype chip of this architecture designed in 90 nm standard cell technology manufactured by TSMC will conclude this contribution.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

FPGA Synthesis of Reconfigurable Modules for FIR Filter

2015 ◽  
Vol 4 (2) ◽  
pp. 63
Author(s):  
Saranya R ◽  
Pradeep C ◽  
Neena Baby ◽  
Radhakrishnan R
Keyword(s):  
Reconfigurable Computing ◽  
Fault Tolerant ◽  
Fir Filter ◽  
Divide And Conquer ◽  
Coarse Grained ◽  
Verilog Hdl ◽  
Detection Mechanism ◽  
Fine Grained ◽  
Dsp Systems ◽  
Important Building Block

Reconfigurable computing for DSP remains an active area to explore as the need for incorporation with more conventional DSP technologies turn out to be obvious. Conventionally, the majority of the work in the area of reconfigurable computing is aimed on fine grained FPGA devices. Over the years, the focus is shifted from bit level granularity to a coarse grained composition. FIR filter remains and persist to be an important building block in various DSP systems. It computes the output by multiplying input samples with a set of coefficients followed by addition. Here multipliers and adders are modeled using the concept of divide and conquer. For developing a reconfiguarble FIR filter, different tap filters are designed as separate reconfigurable modules. Furthermore, there is an additional concern for making the system fault tolerant. A fault detection mechanism is introduced to detect the faults based on the nature of operands. The reconfigurable modules are structurally modeled in Verilog HDL and simulated and synthesized using Xilinx ISE 14.2. A comparison of the device utilization of reconfigurable modules is also presented in this paper by implementing the design on various Virtex FPGA devices.

scholarly journals Significance of Fines in Hot Mix Asphalt Synthesis

2017 ◽  
Vol 6 (1) ◽  
pp. 30-42
Author(s):  
Elvira Kalaitzaki ◽  
George Kollaros ◽  
Antonia Athanasopoulou
Keyword(s):  
Fly Ash ◽  
Hot Mix Asphalt ◽  
Coarse Grained ◽  
Mineral Filler ◽  
Fine Grained ◽  
Particle Contact ◽  
A Value ◽  
Load Carrying ◽  
And Performance

Abstract According to their size, aggregates are classified in coarse grained, fine grained, and fines. The determination of fines content in aggregate materials is very simple and is performed through the aggregate washing during the sieving procedure to define the gradation curve. The very fine material consists of grains having a size lower than 63 μm. The presence of fines directly influences the composition and performance of concrete and asphalt mixtures (e.g. asphalt content, elasticity, fracture). The strength and load carrying capacity of hot mix asphalt (HMA) results from the aggregate framework created through particle-particle contact and interlock. Fines or mineral filler have a role in HMA. The coarse aggregate framework is filled by the sand-sized material and finally by the mineral filler. At some point, the smallest particles lose contact becoming suspended in the binder not having the particle-particle contact that is created by the larger particles. The overall effect of mineral filler in hot mix asphalt specimens has been investigated through a series of laboratory tests. It is clear that a behaviour influenced by the adherence of fines to asphalt film has been developed. The optimum bitumen content requirement in case of stone filler is almost the same as that for fly ash. It has been found that the percentage of fly ash filler is crucial if it exceeds approximately a value of 4%.

scholarly journals Implementation of FPGA based MRPMA for high performance applications

2017 ◽  
Vol 7 (1.5) ◽  
pp. 158
Author(s):  
T. Siva Sankara Phani ◽  
M. Sujatha ◽  
K. Hari Kishore ◽  
M. Durga Prakash
Keyword(s):  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Coarse Grained ◽  
Fast Fourier Transformation ◽  
Discrete Cosine Transformation ◽  
Fine Grained ◽  
Reconfigurable Devices ◽  
Shortest Route ◽  
Domain 3

In the last few decay, Network on Chip’s (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE’s) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.   

scholarly journals A Non-Intrusive, Traffic-Aware Prediction Framework for Power Consumption in Data Center Operations

Energies ◽  
2020 ◽  
Vol 13 (3) ◽  
pp. 663
Author(s):  
Zheng Liu ◽  
Mian Zhang ◽  
Xusheng Zhang ◽  
Yun Li
Keyword(s):  
Power Consumption ◽  
Prediction Model ◽  
Data Center ◽  
Data Centers ◽  
Prediction Performance ◽  
Coarse Grained ◽  
Fine Grained ◽  
Encoding Strategy ◽  
Power Consumption Prediction ◽  
Consumption Prediction

Modern cloud computing relies heavily on data centers, which usually host tens of thousands of servers. Predicting the power consumption accurately in data center operations is crucial for energy optimization. In this paper, we formulate the power consumption prediction at both the fine-grained and coarse-grained level. We carefully discuss the desired properties of an applicable prediction model and propose a non-intrusive, traffic-aware prediction framework for power consumption. We design a character-level encoding strategy for URIs and employ both convolutional and recurrent neural networks to develop a unified prediction model. We use real datasets to simulate requests and analyze the characteristics of the collected power consumption series. Extensive experiments demonstrate that our proposed framework can achieve superior prediction performance compared to other popular leading prediction methods.

scholarly journals Coarse-Grained Reconfigurable Computing with the Versat Architecture

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 669
Author(s):  
João D. Lopes ◽  
Mário P. Véstias ◽  
Rui Policarpo Duarte  ◽  
Horácio C. Neto ◽  
José T. de Sousa 
Keyword(s):  
Reconfigurable Computing ◽  
Coarse Grained ◽  
Reconfigurable Architectures ◽  
Partial Reconfiguration ◽  
Graph Topology ◽  
Reconfigurable Array ◽  
And Performance ◽  
The Right ◽  
Frequency Power

Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.

Correlation between dislocation, grain boundary and interface of duplex SS in stress corrosion cracking(SCC)

1990 ◽  
Vol 48 (4) ◽  
pp. 928-929
Author(s):  
Wang Zheng-fang ◽  
Z.F. Wang
Keyword(s):  
Stainless Steel ◽  
Thermal Cycle ◽  
Secondary Phase ◽  
Corrosion Cracking ◽  
Coarse Grained ◽  
Test Environment ◽  
Fine Grained ◽  
Evaluation Test ◽  
Welding Thermal Cycle ◽  
Micro Analysis

The main purpose of this study highlights on the evaluation of chloride SCC resistance of the material,duplex stainless steel,OOCr18Ni5Mo3Si2 (18-5Mo) and its welded coarse grained zone(CGZ).18-5Mo is a dual phases (A+F) stainless steel with yield strength:512N/mm2 .The proportion of secondary Phase(A phase) accounts for 30-35% of the total with fine grained and homogeneously distributed A and F phases(Fig.1).After being welded by a specific welding thermal cycle to the material,i.e. Tmax=1350°C and t8/5=20s,microstructure may change from fine grained morphology to coarse grained morphology and from homogeneously distributed of A phase to a concentration of A phase(Fig.2).Meanwhile,the proportion of A phase reduced from 35% to 5-10°o.For this reason it is known as welded coarse grained zone(CGZ).In association with difference of microstructure between base metal and welded CGZ,so chloride SCC resistance also differ from each other.Test procedures:Constant load tensile test(CLTT) were performed for recording Esce-t curve by which corrosion cracking growth can be described, tf,fractured time,can also be recorded by the test which is taken as a electrochemical behavior and mechanical property for SCC resistance evaluation. Test environment:143°C boiling 42%MgCl2 solution is used.Besides, micro analysis were conducted with light microscopy(LM),SEM,TEM,and Auger energy spectrum(AES) so as to reveal the correlation between the data generated by the CLTT results and micro analysis.

scholarly journals Power and Performance Evaluation of Memory-Intensive Applications

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4089
Author(s):  
Kaiqiang Zhang ◽  
Dongyang Ou ◽  
Congfeng Jiang ◽  
Yeliang Qiu ◽  
Longchuan Yan
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Power Consumption ◽  
Job Scheduling ◽  
Memory System ◽  
Processor Core ◽  
Memory Efficiency ◽  
And Performance ◽  
Reasonable Use ◽  
Server System

In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation.

Sign in / Sign up

Export Citation Format

Share Document