scholarly journals New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

2011 ◽  
Vol 2011 ◽  
pp. 1-6 ◽  
Author(s):  
Kirti Gupta ◽  
Ranjana Sridhar ◽  
Jaya Chaudhary ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
Positive Feedback ◽  
Cmos Technology ◽  
Performance Comparison ◽  
Power Efficient ◽  
Power Delay Product ◽  
Feedback Source ◽  
Design Techniques ◽  
A Performance

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

AN ULTRA LOW-POWER CURRENT-MODE SENSE AMPLIFIER FOR SRAM APPLICATIONS

2005 ◽  
Vol 14 (05) ◽  
pp. 939-951 ◽  
Author(s):  
ZHI-HUI KONG ◽  
KIAT-SENG YEO ◽  
CHIP-HONG CHANG
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Power Efficient ◽  
Power Characteristics ◽  
Sense Amplifier ◽  
Micro Power ◽  
Power Delay Product

A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

Design and Analysis of Power Efficient TG Based Dual Edge Triggered Flip-Flops with Stacking Technique

2019 ◽  
Vol 29 (08) ◽  
pp. 2050123 ◽  
Author(s):  
Neethu Anna Sabu ◽  
K. Batri
Keyword(s):  
Vlsi Design ◽  
Cmos Technology ◽  
Flip Flop ◽  
Circuit Performance ◽  
Power Efficient ◽  
Transmission Gate ◽  
Double Edge ◽  
Speed Performance ◽  
Layout Area ◽  
Power Delay Product

One of the paramount issues in the field of VLSI design is the rapid increase in power consumption. Therefore, it is necessary to develop power-efficient circuits. Here, three new simple architectures are presented for a Dynamic Double Edge Triggered Flip-flop named as Transistor Count Reduction Flip-flop, S-TCRFF (Series Stacking in TCRFF) and FST in TCRFF (Forced Stacking of Transistor in TCRFF). The first one features a dynamic design comprising of transmission gate in which total transistor count has greatly reduced without affecting the logic, thereby attaining better power and speed performance. For the reduction of static power, two types of stacking called series and forced transistor stacking are applied. The circuits are simulated using Cadence Virtuoso in 45[Formula: see text]nm CMOS technology with a power supply of 1[Formula: see text]V at 500[Formula: see text]MHz when input switching activity is 25%. The simulated results indicated that the new designs (TCRFF, S-TCRFF and FST in TCRFF) excelled in different circuit performance indices like Power-Delay-Product (PDP), Energy-Delay-Product (EDP), average and leakage power with less layout area compared with the performance of nine recently proposed FF designs. The improvement in PDPdq value was up to 89.2% (TCRFF), 89.9% (S-TCRFF) and 90.3% (FST in TCRFF) with conventional transmission gate FF (TGFF).

scholarly journals A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications

2020 ◽  
Vol 29 (14) ◽  
pp. 2050220
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker
Keyword(s):  
Positive Feedback ◽  
Cmos Technology ◽  
Voltage Gain ◽  
Silicon Area ◽  
Power Efficient ◽  
Enhancement Technique ◽  
Op Amp ◽  
Gain Enhancement ◽  
Pvt Variations ◽  
Boosting Technique

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

scholarly journals Low Glitch & Low Power Dual Edge Triggered DType Flip Flops for Integrated Applications

2019 ◽  
Vol 8 (2) ◽  
pp. 5906-5912
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Flip Flop ◽  
Silicon Area ◽  
Low Delay ◽  
Cadence Tool ◽  
Power Delay Product ◽  
Design Paper

This paper presents Dual Edge Triggered (DET) master slave D-Type flip flops for glitch free, low power, low delay, low silicon area and low Power Delay Product (PDP). This DET master slave D-Type flip flops are compared against the existing DET flip flops using 45nm & 180nm CMOS technology which has been simulated using Cadence Virtuoso. The proposed DET master slave D-Type flip flops has reduced the number of transistors in use for operation, which leads to low glitch, low power and low delay design. Paper consist glitch free DET master slave D-Type flip flops analysis for power, delay and PDP. The proposed DET flip flop is also simulated and implemented for 18nm Fin-FET in Cadence Tool.

scholarly journals Full Adder for Low Power Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 2682-2687
Keyword(s):  
Low Power ◽  
Processing System ◽  
Full Adder ◽  
Cmos Technology ◽  
Fundamental Operation ◽  
Dynamic Power ◽  
Power Delay Product ◽  
Electronic Processing

In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.

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