scholarly journals The Potential for a GPU-Like Overlay Architecture for FPGAs

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Jeffrey Kingyens ◽  
J. Gregory Steffan
Keyword(s):  
Graphics Processing Units ◽  
Programming Model ◽  
Instruction Level Parallelism ◽  
Floating Point ◽  
Register Files ◽  
High Level ◽  
Graphics Processing ◽  
Level Parallelism ◽  
Data Level ◽  
Accelerator System

We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overcoming the challenges of port limitations of FPGA block memories as well as memory and pipeline latency. Through simulation of a system that (i) is programmable via NVIDIA's high-levelCglanguage, (ii) supports AMD's CTM r5xx GPU ISA, and (iii) is realizable on an XtremeData XD1000 FPGA-based accelerator system, we demonstrate the potential for such a system to achieve 100% utilization of a deeply pipelined floating-point datapath.

scholarly journals Multiple-Precision BLAS Library for Graphics Processing Units

2020 ◽  
Author(s):  
Konstantin Isupov ◽  
Vladimir Knyazkov
Keyword(s):  
Graphics Processing Units ◽  
Arithmetic Operation ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Data Types ◽  
Rounding Errors ◽  
Multiple Precision ◽  
Graphics Processing ◽  
Point Arithmetic

The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

scholarly journals A Ubiquitous Processor Built-in a Waved Multifunctional Unit

1970 ◽  
Vol 4 (1) ◽  
pp. 1-7
Author(s):  
Masa-aki Fukase ◽  
Tomoaki Sato
Keyword(s):  
Mobile Applications ◽  
High Performance ◽  
Scale Up ◽  
Instruction Scheduling ◽  
Instruction Level Parallelism ◽  
Floating Point ◽  
Ubiquitous Systems ◽  
Wide Range ◽  
Wave Pipelining ◽  
Level Parallelism

In developing cutting edge VLSI processors, parallelism is one of the most important global standard strategies to achieve power conscious high performance. These features are more critical for ubiquitous systems with great demands for multimedia mobile processing. Then, one of most important issues for ubiquitous systems is instruction scheduling, because floating point units indispensable for multimedia mobile applications take longer latency than integer units. Although software parallelism has been inevitable to fully utilize hardware parallelism between regular scalar units, it has been really awkward. Thus, we describe in this article a double scheme to achieve instruction scheduling free ILP (instruction level parallelism) and apply the double scheme to a ubiquitous processor HCgorilla we have so far developed. The double scheme is the multifunctionalization of scalar units and making a resultant multifunctional unit (MFU) wave-pipeline. The multifunctionalization frees the instruction scheduling, and the wave-pipelining recovers the reduction of clock speed to be caused by the scale up of a multifunctional circuit. HCgorilla built-in the waved MFU is promising for wide-range dynamic ILP at a rate higher than regular processors.

scholarly journals Convolving Pre-Trained Convolutional Neural Networks at Various Magnifications to Extract Diagnostic Features for Digital Pathology

2018 ◽  
Author(s):  
John-William Sidhom ◽  
Alexander S. Baras
Keyword(s):  
Deep Learning ◽  
Graphics Processing Units ◽  
Visual Recognition ◽  
Digital Pathology ◽  
Diagnostic Features ◽  
High Level ◽  
Graphics Processing ◽  
Computational Analyses ◽  
Radiology And Pathology

ABSTRACTDeep learning is an area of artificial intelligence that has received much attention in the past few years due to both an increase in computational power with the increased use of graphics processing units (GPU’s) for computational analyses and the performance of these class of algorithms on visual recognition tasks. They have found utility in applications ranging from image search to facial recognition for security and social media purposes. Their continued success has propelled their use across many new domains including the medical field, in areas of radiology and pathology in particular, as these fields are thought to be driven by visual recognition tasks. In this paper, we present an application of deep learning, termed ‘transfer learning’, using ResNet50, a pre-trained convolutional neural network (CNN) to act as a ‘feature-detector’ at various magnifications to identify low and high level features in digital pathology images of various breast lesions for the purpose of classifying them correctly into the labels of normal, benign, in-situ, or invasive carcinoma as provided in the ICIAR 2018 Breast Cancer Histology Challenge (BACH).

Advanced Topics GPU Programming and CUDA Architecture

2016 ◽  
pp. 175-203
Author(s):  
Mainak Adhikari ◽  
Sukhendu Kar
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Programming Model ◽  
Graphics Processing Unit ◽  
Direct Access ◽  
Gpu Programming ◽  
Processing Unit ◽  
Computing Platform ◽  
Cuda Architecture ◽  
Graphics Processing

Graphics processing unit (GPU), which typically handles computation only for computer graphics. Any GPU providing a functionally complete set of operations performed on arbitrary bits can compute any computable value. Additionally, the use of multiple graphics cards in one computer, or large numbers of graphics chips, further parallelizes the already parallel nature of graphics processing. CUDA (Compute Unified Device Architecture) is a parallel computing platform and programming model created by NVIDIA and implemented by the graphics processing units (GPUs). CUDA gives program developers direct access to the virtual instruction set and memory of the parallel computational elements in CUDA GPUs. This chapter first discuss some features and challenges of GPU programming and the effort to address some of the challenges with building and running GPU programming in high performance computing (HPC) environment. Finally this chapter point out the importance and standards of CUDA architecture.

scholarly journals Early Periodic Register Allocation on ILP Processors

2004 ◽  
Vol 14 (02) ◽  
pp. 287-313 ◽  
Author(s):  
Sid-Ahmed-Ali TOUATI ◽  
Christine EISENBEIS
Keyword(s):  
Optimization Method ◽  
Register Allocation ◽  
Software Pipelining ◽  
Instruction Level Parallelism ◽  
Register Files ◽  
Register Pressure ◽  
Good Improvement ◽  
Level Parallelism ◽  
Register Allocator

Register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation as a first step without assuming a schedule lacks the information of interferences between values live ranges. Thus, the register allocator may introduce an excessive amount of false dependences that dramatically reduce the ILP (Instruction Level Parallelism). We present a new theoretical framework for controlling the register pressure before software pipelining. Thus is based on inserting some anti-dependence edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to fix the register pressure, measured as the number of simultaneously alive variables in any schedule. The determination of register and distance reuse is parameterized by the desired minimum initiation interval (MII) as well as by the register pressure constraints - either can be minimized while the other one is fixed. After scheduling, register allocation is done on conventional register sets or on rotating register files. We give an optimal exact model, and an approximation that generalizes the Ning-Gao [22] buffer optimization method. We provide experimental results which show good improvement compared to [22]. Our theoretical model considers superscalar, VLIW and EPIC/IA64 processors.

scholarly journals Massive-Parallel Trajectory Calculations version 2.2 (MPTRAC-2.2): Lagrangian transport simulations on Graphics Processing Units (GPUs)

2021 ◽  
Author(s):  
Lars Hoffmann ◽  
Paul Baumeister ◽  
Zhongyin Cai ◽  
Jan Clemens ◽  
Sabine Griessbach ◽  
...  
Keyword(s):  
Graphics Processing Units ◽  
Large Scale ◽  
Transport Model ◽  
Programming Model ◽  
Meteorological Data ◽  
Transport Processes ◽  
Model Verification ◽  
Lagrangian Transport ◽  
Trajectory Calculations ◽  
Graphics Processing

Lagrangian models are powerful tools to study atmospheric transport processes. However, conducting large-scaleLagrangian transport simulations with many air parcels can become numerically rather costly. In this study, we assessed the potential of exploiting graphics processing units (GPUs) to accelerate Lagrangian transport simulations. We ported the Massive-Parallel Trajectory Calculations (MPTRAC) model to GPUs using the open accelerator (OpenACC) programming model. The trajectory calculations conducted within the MPTRAC model have been fully ported to GPUs, i. e., except for feeding in the meteorological input data and for extracting the particle output data, the code operates entirely on the GPU devices without frequent data transfers between CPU and GPU memory. Model verification, performance analyses, and scaling tests of the MPI/OpenMP/OpenACC hybrid parallelization of MPTRAC have been conducted on the JUWELS Booster supercomputer operated by the Jülich Supercomputing Centre, Germany. The JUWELS Booster comprises 3744 NVIDIA A100 Tensor CoreGPUs, providing a peak performance of 71.0 PFlop/s. As of June 2021, it is the most powerful supercomputer in Europe and listed among the most energy-efficient systems internationally. For large-scale simulations comprising 100 million particles driven by the European Centre for Medium-Range Weather Forecasts’ ERA5 reanalysis, the performance evaluation showed a maximum speedup of a factor of 16 due to the utilization of GPUs compared to CPU-only runs on the JUWELS Booster. In the large-scale GPU run, about 67 % of the runtime is spent on the physics calculations, being conducted on the GPUs. Another 15 % of the runtime is required for file-I/O, mostly to read the ERA5 data from disk. Meteorological data preprocessing on the CPUs also requires about 15 % of the runtime. Although this study identified potential for further improvements of the GPU code, we consider the MPTRAC model to be ready for production runs on the JUWELS Booster in its present form. The GPU code provides a much faster time to solution than the CPU code, which is particularly relevant for near-real-time applications of a Lagrangian transport model

Selective Fault Tolerance for Register Files of Graphics Processing Units

2019 ◽  
Vol 66 (7) ◽  
pp. 1449-1456 ◽  
Author(s):  
Marcio Goncalves ◽  
Fernando Fernandes ◽  
Ivan Lamb ◽  
Paolo Rech ◽  
Jose Rodrigo Azambuja
Keyword(s):  
Fault Tolerance ◽  
Graphics Processing Units ◽  
Register Files ◽  
Graphics Processing

scholarly journals Multicore Challenges and Benefits for High Performance Scientific Computing

2008 ◽  
Vol 16 (4) ◽  
pp. 277-285 ◽  
Author(s):  
Ida M.B. Nielsen ◽  
Curtis L. Janssen
Keyword(s):  
Message Passing ◽  
High Performance ◽  
Programming Model ◽  
Instruction Level Parallelism ◽  
Performance Improvements ◽  
Processor Performance ◽  
Multiple Threads ◽  
Moller Plesset ◽  
Multicore Chips ◽  
Level Parallelism

Until recently, performance gains in processors were achieved largely by improvements in clock speeds and instruction level parallelism. Thus, applications could obtain performance increases with relatively minor changes by upgrading to the latest generation of computing hardware. Currently, however, processor performance improvements are realized by using multicore technology and hardware support for multiple threads within each core, and taking full advantage of this technology to improve the performance of applications requires exposure of extreme levels of software parallelism. We will here discuss the architecture of parallel computers constructed from many multicore chips as well as techniques for managing the complexity of programming such computers, including the hybrid message-passing/multi-threading programming model. We will illustrate these ideas with a hybrid distributed memory matrix multiply and a quantum chemistry algorithm for energy computation using Møller–Plesset perturbation theory.

scholarly journals Bringing heterogeneity to the CMS software framework

2020 ◽  
Vol 245 ◽  
pp. 05009
Author(s):  
Andrea Bocci ◽  
David Dagenhart ◽  
Vincenzo Innocente ◽  
Christopher Jones ◽  
Matti Kortelainen ◽  
...  
Keyword(s):  
Data Processing ◽  
Graphics Processing Units ◽  
Building Blocks ◽  
Current Data ◽  
Level Trigger ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
High Level ◽  
Graphics Processing ◽  
Leadership Class

The advent of computing resources with co-processors, for example Graphics Processing Units (GPU) or Field-Programmable Gate Arrays (FPGA), for use cases like the CMS High-Level Trigger (HLT) or data processing at leadership-class supercomputers imposes challenges for the current data processing frameworks. These challenges include developing a model for algorithms to offload their computations on the co-processors as well as keeping the traditional CPU busy doing other work. The CMS data processing framework, CMSSW, implements multithreading using the Intel Threading Building Blocks (TBB) library, that utilizes tasks as concurrent units of work. In this paper we will discuss a generic mechanism to interact effectively with non-CPU resources that has been implemented in CMSSW. In addition, configuring such a heterogeneous system is challenging. In CMSSW an application is configured with a configuration file written in the Python language. The algorithm types are part of the configuration. The challenge therefore is to unify the CPU and co-processor settings while allowing their implementations to be separate. We will explain how we solved these challenges while minimizing the necessary changes to the CMSSW framework. We will also discuss on a concrete example how algorithms would offload work to NVIDIA GPUs using directly the CUDA API.

scholarly journals OpenCL Performance Evaluation on Modern Multicore CPUs

2015 ◽  
Vol 2015 ◽  
pp. 1-20 ◽  
Author(s):  
Joo Hwan Lee ◽  
Nimit Nigania ◽  
Hyesoon Kim ◽  
Kaushik Patel ◽  
Hyojong Kim
Keyword(s):  
Parallel Programming ◽  
Programming Model ◽  
Data Locality ◽  
Instruction Level Parallelism ◽  
Performance Variation ◽  
Parallel Programming Model ◽  
Data Location ◽  
Space Data ◽  
Level Parallelism ◽  
Multicore Cpus

Utilizing heterogeneous platforms for computation has become a general trend, making the portability issue important. OpenCL (Open Computing Language) serves this purpose by enabling portable execution on heterogeneous architectures. However, unpredictable performance variation on different platforms has become a burden for programmers who write OpenCL applications. This is especially true for conventional multicore CPUs, since the performance of general OpenCL applications on CPUs lags behind the performance of their counterparts written in the conventional parallel programming model for CPUs. In this paper, we evaluate the performance of OpenCL applications on out-of-order multicore CPUs from the architectural perspective. We evaluate OpenCL applications on various aspects, including API overhead, scheduling overhead, instruction-level parallelism, address space, data location, data locality, and vectorization, comparing OpenCL to conventional parallel programming models for CPUs. Our evaluation indicates unique performance characteristics of OpenCL applications and also provides insight into the optimization metrics for better performance on CPUs.

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