scholarly journals A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

2011 ◽  
Vol 2011 ◽  
pp. 1-10 ◽  
Author(s):  
John C. Hoffman ◽  
Marios S. Pattichis
Keyword(s):  
Reconfigurable Computing ◽  
High Speed ◽  
Direct Memory Access ◽  
Operating Conditions ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Memory Controller ◽  
Dynamically Reconfigurable ◽  
Active Feedback ◽  
Time Overhead

Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead. To minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the reconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively limits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the system can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of overclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and temperature are within nominal operating conditions. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5, consists of four different hardware platforms.

scholarly journals Real Time Monitoring of Diesel Engine Injector Waveforms for Accurate Fuel Metering and Control

2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Q. R. Farooqi ◽  
B. Snyder ◽  
S. Anwar
Keyword(s):  
Real Time ◽  
High Speed ◽  
Direct Memory Access ◽  
Operating Conditions ◽  
Start Of Injection ◽  
Field Programmable ◽  
High Speed Data Acquisition ◽  
Correction Table ◽  
High Speed Data ◽  
Injector Pulse

This paper presents the development, experimentation, and validation of a reliable and robust system to monitor the injector pulse generated by an engine control module (ECM) which can easily be calibrated for different engine platforms and then feedback the corresponding fueling quantity to the real-time computer in a closed-loop controller in the loop (CIL) bench in order to achieve optimal fueling. This research utilizes field programmable gate arrays (FPGA) and direct memory access (DMA) transfer capability to achieve high speed data acquisition and delivery. This work is conducted in two stages: the first stage is to study the variability involved in the injected fueling quantity from pulse to pulse, from injector to injector, between real injector stators and inductor load cells, and over different operating conditions. Different thresholds have been used to find out the best start of injection (SOI) threshold and the end of injection (EOI) threshold that capture the injector “on-time” with best reliability and accuracy. Second stage involves development of a system that interprets the injector pulse into fueling quantity. The system can easily be calibrated for various platforms. Finally, the use of resulting correction table has been observed to capture the fueling quantity with highest accuracy.

High Speed Transaction Hardware Channel in Loosely-Coupled Reconfigurable Computing Emulation System

2012 ◽  
Vol 462 ◽  
pp. 456-463
Author(s):  
Bo Wei Zhang ◽  
Guo Chang Gu ◽  
Xing Zhou Zhang ◽  
Dong Liu
Keyword(s):  
Reconfigurable Computing ◽  
High Speed ◽  
Low Cost ◽  
Direct Memory Access ◽  
Maximum Speed ◽  
Prototype System ◽  
Pci Express ◽  
Loosely Coupled ◽  
Computing Model ◽  
Key Features

The loosely-coupled reconfigurable computing model includes the host microprocessor in conjunction with an external stand-alone reconfigurable hardware which takes advantage of low cost in technology and development time. It can work as a fast emulation approach to study reconfigurable computing prototype system. One of the key features of such emulation system is the ability to perform the communication. In this paper, we proposed a high speed hardware channel with direct memory access(DMA) transaction method based on Xilinx ML555 development kit and PCI-express(peripheral component interconnection express) endpoint block IP. Experiments show that both read and write transaction speed in this design meet the theoretical maximum speed.

scholarly journals A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

2012 ◽  
Vol 2012 ◽  
pp. 1-14
Author(s):  
Sascha Mühlbach ◽  
Andreas Koch
Keyword(s):  
Reconfigurable Computing ◽  
High Speed ◽  
Computer Users ◽  
Dynamic Partial Reconfiguration ◽  
Malicious Software ◽  
Computing Platform ◽  
Device Architecture ◽  
Network Platform ◽  
Dedicated Hardware ◽  
A Current

Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and analyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications, is one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both high-speed operation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this work, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we can now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability emulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical aspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing platform.

Diesel Engine Injector Waveform Monitoring in Real-Time for Fuel Efficiency

2012 ◽  
Author(s):  
Q. R. Farooqi ◽  
S. Anwar ◽  
B. Snyder
Keyword(s):  
Real Time ◽  
High Speed ◽  
Fuel Efficiency ◽  
Direct Memory Access ◽  
Operating Conditions ◽  
Start Of Injection ◽  
Field Programmable ◽  
High Speed Data Acquisition ◽  
Correction Table ◽  
Injector Pulse

This paper presents the development, experimentation and validation of a reliable and robust system, which can be easily calibrated for different engine platforms, to monitor the injector pulse generated by an Engine Control Module (ECM) and feedback the corresponding fueling quantity to the real-time computer in a closed-loop Controller in the loop (CIL) bench in order to achieve optimal fueling. This research utilized Field Programmable Gate Arrays (FPGA) and Direct Memory Access (DMA) transfer capability to achieve high speed data acquisition and delivery. The research is conducted in two stages, first stage was to study the variability involved in the injected fueling quantity from pulse to pulse, from injector to injector, between real injector stators and inductor load cells, over different operating conditions. Different thresholds were experimented to find out the best start of injection (SOI) threshold and the end of injection (EOI) threshold that captured the injector “on-time” with best reliability and accuracy. Second stage involved development of a system that interprets the injector pulse into fueling quantity; the system can be easily calibrated to be used over various platforms. Finally, the use of resulting correction table was found to capture the fueling quantity with best accuracy.

Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio

2020 ◽  
pp. 2150042
Author(s):  
Islam Ahmed ◽  
Ahmed Nader Mohieldin ◽  
Hassan Mostafa
Keyword(s):  
Software Defined Radio ◽  
Computer Aided Design ◽  
Functional Verification ◽  
Partial Reconfiguration ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Aided Design

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle.

The on-line use of histogram data for high-speed correction and alignment of electron microscope images

1984 ◽  
Vol 42 ◽  
pp. 556-557
Author(s):  
William Krakow
Keyword(s):  
Power Spectrum ◽  
High Speed ◽  
Direct Memory Access ◽  
Digital Television ◽  
Contrast Transfer Function ◽  
The Past ◽  
High Resolution Tem ◽  
On Line ◽  
Correction Of Astigmatism ◽  
The Fourier Transform

In the past few years on-line digital television frame store devices coupled to computers have been employed to attempt to measure the microscope parameters of defocus and astigmatism. The ultimate goal of such tasks is to fully adjust the operating parameters of the microscope and obtain an optimum image for viewing in terms of its information content. The initial approach to this problem, for high resolution TEM imaging, was to obtain the power spectrum from the Fourier transform of an image, find the contrast transfer function oscillation maxima, and subsequently correct the image. This technique requires a fast computer, a direct memory access device and even an array processor to accomplish these tasks on limited size arrays in a few seconds per image. It is not clear that the power spectrum could be used for more than defocus correction since the correction of astigmatism is a formidable problem of pattern recognition.

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