A Case Study: Quantitative Evaluation of C-Based High-Level Synthesis Systems

2008 ◽  
Vol 2008 (1) ◽  
pp. 685128 ◽  
Author(s):  
Omar Hammami ◽  
Zhoukun Wang ◽  
Virginie Fresse ◽  
Dominique Houzet
Keyword(s):  
Quantitative Evaluation ◽  
High Level Synthesis ◽  
High Level

Case study of an HEVC decoder application using high-level synthesis: intraprediction, dequantization, and inverse transform blocks

2019 ◽  
Vol 28 (03) ◽  
pp. 1
Author(s):  
Manel Kammoun ◽  
Ahmed Ben Atitallah ◽  
Karim M. A. Ali ◽  
Rabie Ben Atitallah
Keyword(s):  
High Level Synthesis ◽  
Inverse Transform ◽  
High Level

scholarly journals Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks

2013 ◽  
Vol 6 (0) ◽  
pp. 122-126 ◽  
Author(s):  
Yuko Hara-Azumi ◽  
Toshinobu Matsuba ◽  
Hiroyuki Tomiyama ◽  
Shinya Honda ◽  
Hiroaki Takada
Keyword(s):  
Quantitative Evaluation ◽  
Resource Sharing ◽  
High Level Synthesis ◽  
High Level

scholarly journals High-Level Synthesis: Productivity, Performance, and Software Constraints

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Yun Liang ◽  
Kyle Rupnow ◽  
Yinan Li ◽  
Dongbo Min ◽  
Minh N. Do ◽  
...  
Keyword(s):  
Stereo Matching ◽  
Feature Matching ◽  
General Purpose ◽  
High Level Synthesis ◽  
Future Directions ◽  
Hardware Implementations ◽  
Rtl Design ◽  
Order Of Magnitude ◽  
High Level

FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4X to 126X speedup over the software version. The stereo matching algorithms achieve between 3.5X and 67.9X speedup over software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

Sign in / Sign up

Export Citation Format

Share Document