scholarly journals Antirandom Testing: A Distance-Based Approach

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Shen Hui Wu ◽  
Sridhar Jandhyala ◽  
Yashwant K. Malaiya ◽  
Anura P. Jayasumana
Keyword(s):  
Vector Space ◽  
Fault Coverage ◽  
Random Testing ◽  
Test Vector ◽  
Bridging Faults ◽  
New Approach ◽  
Maximum Extent ◽  
Total Distance ◽  
Test Vectors

Random testing requires each test to be selected randomly regardless of the tests previously applied. This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. An algorithm for generating antirandom tests is presented. Compared with traditional pseudorandom testing, antirandom testing is found to be very effective when a high-fault coverage needs to be achieved with a limited number of test vectors. The superiority of the new approach is even more significant for testing bridging faults.

scholarly journals Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Fault Coverage ◽  
Test Vector ◽  
Single Event Upset ◽  
Fault Models ◽  
Test Program ◽  
Global Test ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction ◽  
Selection Of

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture

2018 ◽  
Vol 27 (05) ◽  
pp. 1850078 ◽  
Author(s):  
J. Praveen ◽  
M. N. Shanmukha Swamy
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Vlsi Architecture ◽  
Fault Coverage ◽  
Linear Feedback ◽  
Test Vector ◽  
Test Power ◽  
Chip Area ◽  
Test Vector Generator ◽  
Test Vectors

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

2008 ◽  
Vol E91-A (12) ◽  
pp. 3506-3513 ◽  
Author(s):  
Y. HIGAMI ◽  
K. K. SALUJA ◽  
H. TAKAHASHI ◽  
S.-y. KOBAYASHI ◽  
Y. TAKAMATSU
Keyword(s):  
Fault Coverage ◽  
Test Vectors

scholarly journals A New Approach to the Analysis of Pitch-Positions in Professional Soccer

2019 ◽  
Vol 66 (1) ◽  
pp. 143-153 ◽  
Author(s):  
Marek Konefał ◽  
Paweł Chmura ◽  
Tomasz Zając ◽  
Jan Chmura ◽  
Edward Kowalczuk ◽  
...  
Keyword(s):  
Motion Analysis ◽  
Soccer Players ◽  
Motion Analysis System ◽  
Running Speed ◽  
Heat Maps ◽  
New Approach ◽  
Total Distance ◽  
Professional Soccer ◽  
Percentage Share ◽  
Analysis System

Abstract The purpose of the study was to examine how various playing positions affected the number of (and percentage breakdowns for) physical and technical activities of soccer players in the Germany’s Bundesliga. A further objective was to identify and present features distinguishing between the activities of players within the Defender, Midfielder and Forward formations. The study sample comprised 4426 individual match observations of 473 soccer players competing in the Bundesliga during the 2016/2017 domestic season. Data from the Impire AG motion analysis system, and the so-called ”heat maps” it supplies, revealed areas in which players spent most time during a match, with 22 different playing positions on the pitch identified in consequence. Players in the formation comprising Defenders did not differ significantly in relation to the number of accelerations, the number of shots or the percentage of duels won. Furthermore, there were no significant differences among Midfielders in regard to total distance covered, mean running speed, the number of accelerations, the number of duels and the percentage of duels won. Likewise, Forwards did not differ in distances covered at ≥24 km/h, average running speed, the number of sprints, the number of shots, the proportion of on-target passes, the number of duels, or the percentage share of duels won. Irrespective of the formation or position on the pitch, today’s game of soccer also pays great importance to the number of accelerations, as well as the number of duels engaged in, and their effectiveness.

Vector space model for patent documents with hierarchical class labels

2012 ◽  
Vol 38 (3) ◽  
pp. 222-233 ◽  
Author(s):  
Yen-Liang Chen ◽  
Yu-Ting Chiu
Keyword(s):  
Feature Selection ◽  
Vector Space ◽  
Selection Process ◽  
Vector Space Model ◽  
Class Label ◽  
Discriminative Ability ◽  
New Approach ◽  
Space Model ◽  
Patent Documents ◽  
Class Labels

A vector space model (VSM) composed of selected important features is a common way to represent documents, including patent documents. Patent documents have some special characteristics that make it difficult to apply traditional feature selection methods directly: (a) it is difficult to find common terms for patent documents in different categories; and (b) the class label of a patent document is hierarchical rather than flat. Hence, in this article we propose a new approach that includes a hierarchical feature selection (HFS) algorithm which can be used to select more representative features with greater discriminative ability to present a set of patent documents with hierarchical class labels. The performance of the proposed method is evaluated through application to two documents sets with 2400 and 9600 patent documents, where we extract candidate terms from their titles and abstracts. The experimental results reveal that a VSM whose features are selected by a proportional selection process gives better coverage, while a VSM whose features are selected with a weighted-summed selection process gives higher accuracy.

Fault Detection of Bridging Faults in Digital Circuits by Shared Binary Decision Diagram

2010 ◽  
Vol 439-440 ◽  
pp. 1235-1240
Author(s):  
Ling Chen ◽  
Zhong Liang Pan
Keyword(s):  
Digital Circuits ◽  
Binary Decision Diagram ◽  
Test Method ◽  
Bridging Faults ◽  
Binary Decision ◽  
Xor Operation ◽  
Bridging Fault ◽  
Multiple Primary ◽  
Test Vectors ◽  
Logic Functions

A new test generation method for the bridging faults in digital circuits is proposed in this paper, the method is based on shared binary decision diagram. The shared binary decision diagram can represent many logic functions simultaneously by sharing isomorphic subgraphs, it is used to represent the digital circuits with multiple primary outputs. The binary decision diagram is constructed respectively for the normal circuit and faulty circuit having a bridging fault. The test vectors of the bridging fault can be produced by a XOR operation of the two binary decision diagrams. The experimental results on a lot of benchmark circuits demonstrate that the test method proposed in this paper can get the test vectors of the bridging faults if the faults are testable.

scholarly journals Testability-Driven Layout of Combinational Circuits

VLSI Design ◽  
1998 ◽  
Vol 7 (4) ◽  
pp. 347-352
Author(s):  
C. P. Ravikumar ◽  
Nikhil Sharma
Keyword(s):  
Test Generation ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Vector ◽  
Combinational Circuits ◽  
Bridging Faults ◽  
Cpu Time ◽  
On Line ◽  
Placement Algorithm ◽  
Automatic Test Pattern Generator

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

scholarly journals New construction of algebras as quotients

2020 ◽  
Vol 5 (2) ◽  
pp. 53
Author(s):  
José Ramón Játem Lásser
Keyword(s):  
Vector Space ◽  
Natural Number ◽  
Clifford Algebras ◽  
Vector Spaces ◽  
Complex Numbers ◽  
Natural Numbers ◽  
New Approach ◽  
Binary Operations ◽  
Direct Sum ◽  
New Construction

  In this article we have presented a new approach to define algebras using for a natural number k ≥ 2, the set of natural numbers in base k, none of their digits equal to zero. The study was developed in the context of vector R -spaces and the vector space definitions of the formal multiples of any element x of the field R, of the direct sum of vector spaces and binary operations on vector spaces were used. The results obtained were the construction of a vector space denoted by V, on the basis of the particular set of natural numbers in base k mentioned, which allowed novel ways of defining the well-known and very important algebras of complex numbers and that of quaternions on R as quotients of ideals of V, for suitably chosen ideals I. With this new approach and with the help of the vector spaces V, known algebras can be presented in a different way than those found up to now, by using certain ideals of those spaces in their quotient form. The spaces V can be over any field K and other algebras such as Clifford algebras can be constructed using this procedure.   Keywords: Algebras, Quotients in algebras, Complex numbers and quaternions as quotients of algebras.   Abstract En este artículo se ha presentado un nuevo enfoque para definir álgebras usando para un número natural k ≥ 2, el conjunto de números naturales en base k, ninguno de sus dígitos iguales a cero. El estudio se desarrolló en el contexto de los R-espacios vectoriales y se usaron las definiciones de espacio vectorial de los múltiplos formales de un elemento cualquiera x del cuerpo R, de la suma directa de espacios vectoriales y operaciones binarias sobre espacios vectoriales. Los resultados obtenidos fueron la construcción de un espacio vectorial denotado por V, sobre la base del particular conjunto de números naturales en base k mencionado, que permitió novedosas formas de definir las conocidas y muy importantes álgebras de los números complejos y la de los cuaterniones sobre R como cocientes de ideales de V, para ideales I convenientemente elegidos. Con este nuevo enfoque y con la ayuda de los espacios vectoriales V se pueden presentar álgebras conocidas de manera distinta a las encontradas hasta ahora, al usar en su forma de cociente ciertos ideales de esos espacios V. Los espacios V pueden ser sobre cualquier cuerpo K y otras álgebras como las álgebras de Clifford se pueden construir usando este procedimiento.   Palabras claves: Algebras, cocientes en álgebras, Números complejos y quaterniones como cocientes en álgebras.  

scholarly journals An Extension of the VSM Documents Representation

2017 ◽  
Vol 12 (3) ◽  
pp. 402
Author(s):  
Lucian Nicolae Vintan ◽  
Daniel Ionel Morariu ◽  
Radu George Cretulescu ◽  
Maria Vintan
Keyword(s):  
Vector Space ◽  
Clustering Algorithms ◽  
Vector Space Model ◽  
Bag Of Words ◽  
New Approach ◽  
Parts Of Speech ◽  
Space Model ◽  
Part Of Speech ◽  
Different Parts ◽  
Hyper Space

In this paper we will present a new approach regarding the documents representation in order to be used in classification and/or clustering algorithms. In our new representation we will start from the classical "bag-of-words" representation but we will augment each word with its correspondent part-of-speech. Thus we will introduce a new concept called hyper-vectors where each document is represented in a hyper-space where each dimension is a different part-of-speech component. For each dimension the document is represented using the Vector Space Model (VSM). In this work we will use only five different parts of speech: noun, verb, adverb, adjective and others. In the hyper-space each dimension has a different weight. To compute the similarity between two documents we have developed a new hyper-cosine formula. Some interesting classification experiments are presented as validation cases.

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