scholarly journals High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-13 ◽  
Author(s):  
Ethiopia Nigussie ◽  
Teijo Lehtonen ◽  
Sampo Tuuna ◽  
Juha Plosila ◽  
Jouni Isoaho
Keyword(s):  
Power Consumption ◽  
Long Range ◽  
High Performance ◽  
Phase 1 ◽  
Current Mode ◽  
Wire Length ◽  
Long Distance ◽  
Two Phase ◽  
Worst Case ◽  
Voltage Mode

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.

scholarly journals On Rectilinear Distance-Preserving Trees

VLSI Design ◽  
1998 ◽  
Vol 7 (1) ◽  
pp. 15-30
Author(s):  
Gustavo E. Téllez ◽  
Majid Sarrafzadeh
Keyword(s):  
Approximation Algorithm ◽  
Heuristic Algorithm ◽  
Time Complexity ◽  
High Performance ◽  
Exact Algorithm ◽  
Wire Length ◽  
Worst Case ◽  
Rectilinear Distance ◽  
Source To Sink ◽  
Linear Delay

Given a set of terminals on the plane N={s,ν1,…,νn}, with a source terminal s, a Rectilinear Distance-Preserving Tree (RDPT) T(V, E) is defined as a tree rooted at s, connecting all terminals in N. An RDPT has the property that the length of every source to sink path is equal to the rectilinear distance between that source and sink. A Min- Cost Rectilinear Distance-Preserving Tree (MRDPT) minimizes the total wire length while maintaining minimal source to sink linear delay, making it suitable for high performance interconnect applications.This paper studies problems in the construction of RDPTs, including the following contributions. A new exact algorithm for a restricted version of the problem in one quadrant with O(n2) time complexity is proposed. A novel heuristic algorithm, which uses optimally solvable sub-problems, is proposed for the problem in a single quadrant. The average and worst-case time complexity for the proposed heuristic algorithm are O(n3/2) and O(n3), respectively. A 2-approximation of the quadrant merging problem is proposed. The proposed algorithm has time complexity O(α2T(n)+α3) for any constant α > 1, where T(n) is the time complexity of the solution of the RDPT problem on one quadrant. This result improves over the best previous quadrant merging solution which has O(n2T(n)+n3) time complexity.We test our algorithms on randomly uniform point sets and compare our heuristic RDPT construction against a Minimum Cost Rectilinear Steiner (MRST) tree approximation algorithm. Our results show that RDPTs are competitive with Steiner trees in total wire-length when the number of terminals is less than 32. This result makes RDPTs suitable for VLSI routing applications. We also compare our algorithm to the Rao-Shor RDPT approximation algorithm obtaining improvements of up to 10% in total wirelength. These comparisons show that the algorithms proposed herein produce promising results.

scholarly journals Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1821
Author(s):  
Sandy A. Wasif ◽  
Salma Hesham ◽  
Diana Goehringer ◽  
Klaus Hofmann ◽  
Mohamed A. Abd El Ghany
Keyword(s):  
Power Consumption ◽  
Double Layer ◽  
Energy Efficient ◽  
High Performance ◽  
Data Transfer ◽  
Low Frequency ◽  
Asynchronous Circuit ◽  
Two Phase ◽  
Phase Layer ◽  
On Chip

A network-on-chip (NoC) offers high performance, flexibility and scalability in communication infrastructure within multi-core platforms. However, NoCs contribute significantly to the overall system’s power consumption. The double-layer energy efficient synchronous-asynchronous circuit-switched NoC (CS-NoC) is proposed to enhance the power utilization. To reduce the dynamic power consumption, single-rail asynchronous protocols are utilized. The two-phase and four-phase encoding algorithms are analyzed to determine the most efficient technique. For the data layer, the two asynchronous protocols reduced the power consumption by 80%, with an increase in latency when compared with the fully synchronous protocol. However, the two-phase single-rail protocol had better performance compared with the four-phase protocol by 38%, with the same power consumption and a slight increase in area of 5%. Based on this conducted analysis, the asynchronous two-phase layer had significant power reduction yet operated at a moderate frequency. Therefore, the proposed NoC is divided into two data transfer layers with a single control layer. The data transfer layers are designed using synchronous and asynchronous protocols. The synchronous layer is designated to high-frequency loads, and the asynchronous layer is confined to low-frequency loads. The switching between the layers creates a trade-off between the maximum allowed frequency and the power consumption. The proposed NoC reduces the overall power consumption by 23% when compared with recent previous work. The NoC maintains the same system performance with an 8% area increase over the fully synchronous double-layer in the literature.

scholarly journals High-Performance Long Range-Based Medium Access Control Layer Protocol

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1273
Author(s):  
Yang Liu ◽  
Lei Liu ◽  
Jiacheng Liang ◽  
Jin Chai ◽  
Xuemei Lei ◽  
...  
Keyword(s):  
Access Control ◽  
Medium Access Control ◽  
Long Range ◽  
Data Transmission ◽  
Multiple Access ◽  
High Performance ◽  
Medium Access ◽  
Long Distance ◽  
Heavy Load ◽  
Code Division Multiple

Long Range (LoRa) has become one of the most promising physical layer technologies for the Internet of Things (IoT) ecosystem. Although it manifests low-power consumption and long-distance communication, LoRa encounters a large number of collisions in the IoT environment, which severely affects the system’s throughput and delay performance. In this paper, a code division carrier sense multiple access (CD/CSMA) protocol that resolves the traditional channel collision problem and implements multi-channel transmission is proposed for the LoRa medium access control (MAC) layer. To reduce data transmission delay and maximize the throughput of the system, the adaptive p-persistent CSMA protocol divides the channel load into four states and dynamically adjusts the data transmission probability. Then, to reduce channel collisions significantly, the code division multiple access (CDMA) protocol is performed on different channel states. Moreover, the combination of the proposed adaptive p-persistent CSMA protocol and the CDMA successfully reduces the number of data retransmissions and makes LoRa more stable. The simulation results demonstrate that the proposed adaptive p-persistent CD/CSMA protocol can achieve near-optimal and occasionally even better performance than some conventional MAC protocols, especially in a heavy load channel.

scholarly journals Structural Health Monitoring system with Narrowband IoT and MEMS sensors

2021 ◽  
Author(s):  
Davide Brunelli ◽  
Flavio Di Nuzzo ◽  
Tommaso Polonelli ◽  
Luca Benini
Keyword(s):  
Power Consumption ◽  
Modal Analysis ◽  
Long Range ◽  
Sensor Node ◽  
Low Cost ◽  
Experimental Tests ◽  
Cost Effective ◽  
Wireless Sensor Node ◽  
Mems Sensors ◽  
Long Distance

We propose a low-cost wireless sensor node specifically designed to support modal analysis over extended periods of time with long-range connectivity at low power consumption. Our design uses very cost-effective MEMS accelerometers and exploits the Narrowband IoT protocol (NB-IoT) to establish long-distance connection with 4G infrastructure networks. Long-range wireless connectivity, cabling-free installation and multi-year lifetime are a unique combination of features, not available, to the best of our knowledge, in any commercial or research device. We discuss in detail the hardware architecture and power management of the node. Experimental tests demonstrate a lifetime of more than ten years with a 17000 mAh battery or completely energy-neutral operation with a small solar panel (60 mm x 120 mm). Further, we validate measurement accuracy and confirm the feasibility of modal analysis with the MEMS sensors: compared with a high-precision instrument based on a piezoelectric transducer, our sensor node achieves a maximum difference of 0.08% at a small fraction of the cost and power consumption. <br> <br>

scholarly journals Structural Health Monitoring system with Narrowband IoT and MEMS sensors

2021 ◽  
Author(s):  
Davide Brunelli ◽  
Flavio Di Nuzzo ◽  
Tommaso Polonelli ◽  
Luca Benini
Keyword(s):  
Power Consumption ◽  
Modal Analysis ◽  
Long Range ◽  
Sensor Node ◽  
Low Cost ◽  
Experimental Tests ◽  
Cost Effective ◽  
Wireless Sensor Node ◽  
Mems Sensors ◽  
Long Distance

We propose a low-cost wireless sensor node specifically designed to support modal analysis over extended periods of time with long-range connectivity at low power consumption. Our design uses very cost-effective MEMS accelerometers and exploits the Narrowband IoT protocol (NB-IoT) to establish long-distance connection with 4G infrastructure networks. Long-range wireless connectivity, cabling-free installation and multi-year lifetime are a unique combination of features, not available, to the best of our knowledge, in any commercial or research device. We discuss in detail the hardware architecture and power management of the node. Experimental tests demonstrate a lifetime of more than ten years with a 17000 mAh battery or completely energy-neutral operation with a small solar panel (60 mm x 120 mm). Further, we validate measurement accuracy and confirm the feasibility of modal analysis with the MEMS sensors: compared with a high-precision instrument based on a piezoelectric transducer, our sensor node achieves a maximum difference of 0.08% at a small fraction of the cost and power consumption. <br> <br>

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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