scholarly journals A Sea-of-Gates Style FPGA Placement Algorithm

VLSI Design ◽  
1996 ◽  
Vol 4 (4) ◽  
pp. 293-307
Author(s):  
Kalapi Roy ◽  
Bingzhong (David) Guan ◽  
Carl Sechen
Keyword(s):  
Chip Area ◽  
Field Programmable ◽  
Fpga Placement ◽  
Programmable Gate Arrays ◽  
Placement Algorithm ◽  
Two Phases ◽  
Fixed Cell ◽  
Flexible Architectures ◽  
Design Style ◽  
Global Placement

Field Programmable Gate Arrays (FPGAs) have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style) such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool) developed specifically for this architecture.

Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area

2017 ◽  
Vol 26 (10) ◽  
pp. 1750154 ◽  
Author(s):  
Armin Belghadr ◽  
Ali Jahanian
Keyword(s):  
Integrated Circuits ◽  
Semiconductor Industry ◽  
Three Dimensional ◽  
Design Flow ◽  
Chip Area ◽  
Monolithically Integrated ◽  
Timing Closure ◽  
Field Programmable ◽  
Fpga Placement ◽  
Placement Algorithm

By scaling the semiconductor industry to nano-scale era, design and prototyping cost of cell-based Application-Specific Integrated Circuits (ASICs) becomes more expensive and it makes Field Programmable Gate Arrays (FPGAs) more popular among designers. However, there is a gap between FPGAs and ASICs in terms of timing, dynamic power consumption and logic density. Three-dimensional integration, particularly in the full monolithic process, has been considered as a promising solution to reduce the performance gap of ASICs and FPGAs. In this paper, two new architectures for the monolithically integrated 3D-FPGAs are introduced. In order to exploit the great potentials of the suggested architectures, a new three-dimensional FPGA placement algorithm is proposed thereafter. The proposed placement algorithm, named JABE, is the first of its kind that enables designers to take advantages of the large number of vertical interconnections in the monolithically stacked 3D-FPGAs. Our experiments show a 24% timing improvement for the new architectures and CAD algorithms compared with the conventional TSV-based 3D-FPGAs and design flows. In addition, improvements in terms of the total wirelength and area footprint are reported for the proposed placement algorithms and new architectures.

scholarly journals Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

2013 ◽  
Vol 8 (1) ◽  
pp. 54-63
Author(s):  
Duarte L. Oliveira ◽  
Lester A. Faria ◽  
Eduardo Lussari
Keyword(s):  
Timing Analysis ◽  
Logic Synthesis ◽  
Major Drawback ◽  
Asynchronous Logic ◽  
Gate Arrays ◽  
Globally Asynchronous Locally Synchronous ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Design Style

Contemporary digital systems must be based on the “System-on-Chip – SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays). However the implementation of asynchronous interfaces (asynchronous wrapper – AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style, which is based on asynchronous controllers providing communication between modules (called ports), port controllers are subject to essentialhazard when implemented in FPGAs. In this context, this paper proposes a new asynchronous GALS wrapper architecture, suitable for implementations in any kind of FPGAs. The proposed port controllers showed to be essential-hazard-free, not needing any special cares in implementation concerning to LUTs choice. Additional advantages of the proposed architecture are: total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; the ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and the ports interact with environment in Ib/Ob Mode, not needing a timing analysis. Simulation results show the applicability of the proposed architecture and lead to its practical implementations in FPGAs.

A Novel Puzzle Based Compaction (PBC) Strategy for Enhancing the Utilization of Reconfigurable Resources

2012 ◽  
pp. 287-318
Author(s):  
Ahmed I. Saleh
Keyword(s):  
Response Times ◽  
Field Programmable Gate Arrays ◽  
Chip Area ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Run Time ◽  
High Penalty ◽  
Independent Tasks

Partially reconfigurable field programmable gate arrays (FPGAs) can accommodate several independent tasks simultaneously. FPGA, as all reconfigurable chips, relies on the “host-then-compact-when-needed” strategy. Accordingly, it should have the ability to both place incoming tasks at run time and compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations problem, trying to move running tasks closer to each other in order to free a sufficient area for new tasks. However, compaction conditions the suspension of the running tasks, which introduces a high penalty. In order to increase the chip area utilization as well as not affecting the response times of tasks, efficient compaction techniques become increasingly important. Unfortunately, traditional compaction techniques suffer from a variety of faults. This paper introduces a novel Puzzle Based Compaction (PBC) technique that is a shape aware technique, which takes the tasks shapes into consideration. In this regard, it succeeded not only to eliminate the internal fragmentations but also to minimize the external fragmentations. This paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by accommodating a set of tasks inside the reconfigurable chip.

A Novel Puzzle Based Compaction (PBC) Strategy for Enhancing the Utilization of Reconfigurable Resources

2010 ◽  
Vol 1 (4) ◽  
pp. 34-70
Author(s):  
Ahmed I. Saleh
Keyword(s):  
Response Times ◽  
Field Programmable Gate Arrays ◽  
Chip Area ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Run Time ◽  
High Penalty ◽  
Independent Tasks

Partially reconfigurable field programmable gate arrays (FPGAs) can accommodate several independent tasks simultaneously. FPGA, as all reconfigurable chips, relies on the “host-then-compact-when-needed” strategy. Accordingly, it should have the ability to both place incoming tasks at run time and compact the chip whenever needed. Compaction is a proposed solution to alleviate external fragmentations problem, trying to move running tasks closer to each other in order to free a sufficient area for new tasks. However, compaction conditions the suspension of the running tasks, which introduces a high penalty. In order to increase the chip area utilization as well as not affecting the response times of tasks, efficient compaction techniques become increasingly important. Unfortunately, traditional compaction techniques suffer from a variety of faults. This paper introduces a novel Puzzle Based Compaction (PBC) technique that is a shape aware technique, which takes the tasks shapes into consideration. In this regard, it succeeded not only to eliminate the internal fragmentations but also to minimize the external fragmentations. This paper develops a novel formula, which is the first not to estimate, but to exactly calculate the amount of external fragmentations generated by accommodating a set of tasks inside the reconfigurable chip.

scholarly journals FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load

Energies ◽  
2021 ◽  
Vol 14 (8) ◽  
pp. 2108
Author(s):  
Mohamed Yassine Allani ◽  
Jamel Riahi ◽  
Silvano Vergura ◽  
Abdelkader Mami
Keyword(s):  
Fuzzy Logic ◽  
Hybrid System ◽  
High Voltage ◽  
Field Programmable Gate Arrays ◽  
Energy System ◽  
Maximum Power ◽  
Hybrid Energy ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.

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