An Improved Data Flow Architecture for Logic Simulation Acceleration

The high degree of parallelism in the simulation of digital VLSI systems can be utilized by a data flow architecture to reduce the enormous simulation times. The existing logic simulation accelerators based on the data flow principle use a static data flow architecture along with a timing wheel mechanism to implement the event driven simulation algorithm. The drawback in this approach is that the timing wheel becomes a bottleneck to high simulation throughput. Other shortcomings of the existing architecture are the high communication overhead in the arbitration and distribution networks, and reduced pipelining due to a static data flow architecture. To overcome these, three major improvements are made to the design of a classical data flow based logic simulation accelerator. These include:1) A novel and efficient technique for implementing a pseudo-dynamic data flow architecture to increase pipelining.2) Implementation of a modified distributed event driven simulation algorithm.3) Localized processors for fast evaluation of small primitives.