Analog Parameters of Strained Non-Rectangular Triple Gate FinFETs

2019 ◽  
Vol 31 (1) ◽  
pp. 21-28
Author(s):  
Rudolf T. Bühler ◽  
Renato C. Giacomini ◽  
João A. Martino
Keyword(s):  
Analog Parameters

scholarly journals The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs

2017 ◽  
Vol 64 (9) ◽  
pp. 3595-3600 ◽  
Author(s):  
Caio C. M. Bordallo ◽  
Joao Antonio Martino ◽  
Paula G. D. Agopian ◽  
Alireza Alian ◽  
Yves Mols ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Analog Parameters

Ground Plane influence on UTBB SOI nMOSFET analog parameters

2015 ◽  
Author(s):  
Vitor T. Itocazu ◽  
Victor Sonnenberg ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
Joao A. Martino
Keyword(s):  
Ground Plane ◽  
Analog Parameters

scholarly journals Boosting the MOSFETs Matching by Using Diamond Layout Style

2017 ◽  
Vol 12 (1) ◽  
pp. 33-41
Author(s):  
Vinicius Vono Peruzzi ◽  
Christian Renaux ◽  
Denis Flandre ◽  
Salvador Pinillos Gimenez
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Cmos Integrated Circuits ◽  
Alternative Technique ◽  
Figures Of Merit ◽  
Analog Parameters

This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETs’ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.

Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

2009 ◽  
Vol 24 (11) ◽  
pp. 115017 ◽  
Author(s):  
R T Bühler ◽  
R Giacomini ◽  
M A Pavanello ◽  
J A Martino
Keyword(s):  
Cross Section ◽  
Cross Section Shape ◽  
Section Shape ◽  
Analog Parameters

Analog parameters of MuGFET devices with different source/drain engineering

2012 ◽  
Author(s):  
M. Galeti ◽  
M. Rodrigues ◽  
J. A. Martino ◽  
N. Collaert ◽  
E. Simoen ◽  
...  
Keyword(s):  
Analog Parameters

scholarly journals Design and Performance Analysis of Hybrid SELBOX Junctionless FinFET

2019 ◽  
pp. 25-32
Keyword(s):  
Current Gain ◽  
Thin Body ◽  
Feature Size ◽  
Self Heating ◽  
Gate Capacitance ◽  
Inversion Region ◽  
And Performance ◽  
Better Than ◽  
Analog Parameters ◽  
Intrinsic Gain

In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed using numerical simulations. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and hybrid (or inverted-T) JLFinFETs (JLTs). The ION of the hybrid SELBOX- JLFinFET is 1.43x times better than the ION of the JLT due to the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg), and intrinsic gain (A0), are evaluated. The proposed device with a minimum feature size of 10nm exhibited better TGF, fT, VEA, and A0 in the deep-inversion region of operation.

scholarly journals Influence of Fin Shape and Temperature on Conventional and Strained MuGFETs’ Analog Parameters

2011 ◽  
Vol 6 (2) ◽  
pp. 94-101
Author(s):  
Rudolf T. Buhler ◽  
Renato Giacomini ◽  
João Antonio Martino
Keyword(s):  
Harmonic Distortion ◽  
Drain Current ◽  
Strained Silicon ◽  
Voltage Gain ◽  
Unity Gain ◽  
Voltage Saturation ◽  
Body Cross Section ◽  
Rectangular Body ◽  
Analog Parameters ◽  
Fin Shape

This work evaluates two important technological variations of Triple-Gate FETs: the use of strained silicon and the occurrence of non-rectangular body cross-section. The anaysis is focused on the electrical parameters for analog applications, and covers a temperature range from 150 K to 400 K. The comparison of the intrinsic voltage gain between the different trapezoidal fin shapes showed that the fin shape can have a major role in some analog parameters than the use of the strained silicon technology, helping to improve those parameters under certain circumstances. The highest intrinsic voltage gains were obtained for strained devices with top fin width larger than bottom at low temperature. Besides the intrinsic voltage gain, were also studied: the threshold voltage, subthreshold swing, drain induced barrier lowering, channel resistance, total harmonic distortion, transconductance, transconductance to drain current ratio, output conductance, Early voltage, drain voltage saturation and unity gain frequency.

Comprehensive investigation on RF/analog parameters in ferroelectric tunnel FET

2021 ◽  
Author(s):  
Rajesh Saha ◽  
Rupam Goswami ◽  
Brinda Bhowmick ◽  
Srimanta Baishya
Keyword(s):  
Transfer Characteristic ◽  
Comprehensive Investigation ◽  
Gate Capacitance ◽  
Tunnel Fet ◽  
Saturation Polarization ◽  
Analog Performance ◽  
Wide Range ◽  
Ferroelectric Layer ◽  
Output Conductance ◽  
Analog Parameters

Abstract In this paper, the effect of ferroelectric layer thickness (tFE), coercive field (Ec), remnant polarization (Pr), and saturation polarization (Ps) on transfer characteristic is highlighted for a Ferroelectric Tunnel FET (Fe-TFET) through a commercial TCAD simulator. Further, we have reported the RF/analog parameters like transconductance (gm), output conductance (gd), gain (gm/gd), gate capacitance (Cgg), and cut off frequency (ft) for wide range of FE parameters in Fe-TFET. Improved RF/analog performance and transfer characteristic are obtained for low value of tFE, Pr, Ec, whereas, these behavior is degraded at high value of Ps.

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