Back-Gate Influence on the Mobility Behavior in Ultrathin FD SOI Devices

2019 ◽  
Vol 23 (1) ◽  
pp. 583-589
Author(s):  
Carolina D. Dos Santos ◽  
Loan Pham-Nguyen ◽  
Sorin Cristoloveanu ◽  
Claire Fenouillet-Béranger ◽  
João A. Martino
Keyword(s):  
Back Gate ◽  
Mobility Behavior ◽  
Soi Devices

Analysis and Optimization of the Back-Gate Effect on Lateral High-Voltage SOI Devices

2005 ◽  
Vol 52 (7) ◽  
pp. 1649-1655 ◽  
Author(s):  
S. Schwantes ◽  
T. Florian ◽  
T. Stephan ◽  
M. Graf ◽  
V. Dudek
Keyword(s):  
High Voltage ◽  
Back Gate ◽  
Gate Effect ◽  
Soi Devices

Analysis of the Back-Gate Effect on the On-State Breakdown Voltage of Smartpower SOI Devices

2006 ◽  
Author(s):  
Stefan Schwantes ◽  
Josef Furthaler ◽  
Bernd Schauwecker ◽  
Franz Dietz ◽  
Michael Graf ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Back Gate ◽  
Gate Effect ◽  
Soi Devices ◽  
State Breakdown

Analysis of the Back-Gate Effect on the on-State Breakdown Voltage of Smartpower SOI Devices

2006 ◽  
Vol 6 (3) ◽  
pp. 377-385 ◽  
Author(s):  
S. Schwantes ◽  
J. Furthaler ◽  
B. Schauwecker ◽  
F. Dietz ◽  
M. Graf ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Back Gate ◽  
Gate Effect ◽  
Soi Devices ◽  
State Breakdown

Effect of the back gate conduction on 0.25 μm SOI devices

2002 ◽  
Author(s):  
J.L. Pelloie ◽  
D.K. Sadana ◽  
H.J. Hovel ◽  
G.G. Shahidi ◽  
J. Warnock ◽  
...  
Keyword(s):  
Back Gate ◽  
Soi Devices

The advancement of silicon-on-insulator (SOI) devices and their basic properties

2020 ◽  
Vol 23 (3) ◽  
pp. 227-252
Author(s):  
T.E. Rudenko ◽  
◽  
A.N. Nazarov ◽  
V.S. Lysenko ◽  
◽  
...  
Keyword(s):  
Silicon On Insulator ◽  
Basic Properties ◽  
Soi Devices

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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