Low-Damage SF[sub 6] Plasma-Etching Condition for Planar GaN HEMTs

2009 ◽  
Vol 156 (1) ◽  
pp. H68 ◽  
Author(s):  
JeoungChill Shim ◽  
Akio Miyao ◽  
Hiroyuki Sakurai ◽  
Keiichi Matsushita ◽  
Ken Onodera ◽  
...  
Keyword(s):  
Plasma Etching ◽  
Etching Condition ◽  
Gan Hemts

Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

1996 ◽  
Vol 54 ◽  
pp. 944-945
Author(s):  
Richard G. Sartore
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Microwave Integrated Circuits ◽  
Monolithic Microwave Integrated Circuits ◽  
Thick Gold ◽  
Gaas Devices ◽  
Source Distance ◽  
Margin Of Error ◽  
Dimensional Measurements ◽  
Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study

1990 ◽  
Vol 48 (4) ◽  
pp. 566-567
Author(s):  
F. Banhart ◽  
F.O. Phillipp ◽  
R. Bergmann ◽  
E. Czech ◽  
M. Konuma ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Liquid Phase ◽  
Plasma Etching ◽  
Liquid Phase Epitaxy ◽  
Three Dimensional ◽  
Microscopical Study ◽  
Sample Temperature ◽  
Structural Defects ◽  
Si Substrates ◽  
Etched Surface

Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

Metal-Assisted Plasma Etching of Silicon: A Liquid-Free Alternative to MACE

2018 ◽  
Author(s):  
Julia Sun ◽  
Benjamin Almquist
Keyword(s):  
Liquid Phase ◽  
Plasma Etching ◽  
Chemical Etching ◽  
Gold Films ◽  
Metallic Films ◽  
Au Catalyst ◽  
Feed Concentration ◽  
Catalytic Activities ◽  
Metal Assisted Chemical Etching ◽  
Complex Nanostructures

For decades, fabrication of semiconductor devices has utilized well-established etching techniques to create complex nanostructures in silicon. Of these, two of the most common are reactive ion etching in the gaseous phase and metal-assisted chemical etching (MACE) in the liquid phase. Though these two methods are highly established and characterized, there is a surprising scarcity of reports exploring the ability of metallic films to catalytically enhance the etching of silicon in dry plasmas via a MACE-like mechanism. Here, we discuss a <u>m</u>etal-<u>a</u>ssisted <u>p</u>lasma <u>e</u>tch (MAPE) performed using patterned gold films to catalyze the etching of silicon in an SF<sub>6</sub>/O<sub>2</sub> mixed plasma, selectively increasing the rate of etching by over 1000%. The degree of enhancement as a function of Au catalyst configuration and relative oxygen feed concentration is characterized, along with the catalytic activities of other common MACE metals including Ag, Pt, and Cu. Finally, methods of controlling the etch process are briefly explored to demonstrate the potential for use as a liquid-free fabrication strategy.

Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors

2006 ◽  
Author(s):  
Vinod Narang ◽  
P. Muthu ◽  
J.M. Chin ◽  
Vanissa Lim
Keyword(s):  
Plasma Etching ◽  
Data Interpretation ◽  
Parameters Optimization ◽  
Scanning Capacitance Microscopy ◽  
Microscopy Technique ◽  
Thermal Oxide ◽  
Specific Analysis ◽  
Thin Oxide ◽  
P Type ◽  
Uv Ozone

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

Infrared and Visible—Near Infrared Electroluminescence Developments for FA in AlGaN/GaN HEMTS on SiC

2010 ◽  
Author(s):  
M. Bouya ◽  
D. Carisetti ◽  
J.C. Clement ◽  
N. Malbert ◽  
N. Labat ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Near Infrared ◽  
High Electron Mobility Transistor ◽  
Low Noise ◽  
Civil Defense ◽  
Base Stations ◽  
Infrared Range ◽  
High Electron ◽  
Radar Applications ◽  
Gan Hemts

Abstract HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. They are crucial components for the development of base stations in the telecommunications networks and for civil, defense and space radar applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by standard (Visible-NIR) and Infrared (range of wavelength: 3-5 µm) electroluminescence techniques. Its complementarities and efficiency have been demonstrated through two case studies.

МОДУЛЬНОЕ ПРОЕКТИРОВАНИЕ ВАКУУМНЫХ УСТАНОВОК ДЛЯ МИКРОЭЛЕКТРОННЫХ ТЕХНОЛОГИЙ

2020 ◽  
Vol 96 (3s) ◽  
pp. 489-493
Author(s):  
М.Г. Бирюков ◽  
В.В. Одиноков ◽  
В.В. Панин ◽  
В.М. Долгополов ◽  
А.В. Шубников
Keyword(s):  
Plasma Etching ◽  
Vacuum Plasma ◽  
Loading And Unloading ◽  
Cluster Type

Представлен модульный принцип создания вакуумно-плазменного оборудования для микроэлектронных технологий с использованием различных вариантов загрузки-выгрузки пластин в рабочий модуль (реактор): установки с поштучной ручной загрузкой-выгрузкой пластин, с поштучной загрузкой-выгрузкой пластин из шлюзовой камеры манипулятором, с поштучной загрузкой-выгрузкой пластин манипулятором из кассеты в кассету в шлюзовой камере, а также оборудование кластерного типа. Рабочие модули установок обеспечивают высокие требования к процессам плазмохимического травления. The paper presents modular principle of creating vacuum-plasma equipment for microelectronic technologies by using various options for loading and unloading wafers into a working module (reactor): systems with single manual loading and unloading wafers, with single loading and unloading wafers from a loadlock by a manipulator, with single loading and unloading wafers with a manipulator from a cassette-to-cassette in a loadlock, as well as cluster type equipment. Working modules of systems provide high requirements to the processes of plasma etching.

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