Low Temperature Boron Activation in Amorphous Germanium for Three Dimensional Integrated Circuits (3D-ICs) using Ni-induced Crystallization

2019 ◽  
Vol 16 (10) ◽  
pp. 909-916
Author(s):  
Jin-Hong Park ◽  
Munehiro Tada ◽  
Hyun-Yong Yu ◽  
Duygu Kuzum ◽  
Yeul Na ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Three Dimensional ◽  
Amorphous Germanium ◽  
3D Ics ◽  
Induced Crystallization

Development of Backside Buried Metal Layer Technology for 3D-ICs

2019 ◽  
Vol 2019 (1) ◽  
pp. 000268-000273
Author(s):  
Naoya Watanabe ◽  
Yuuki Araga ◽  
Haruo Shimamoto ◽  
Katsuya Kikuchi ◽  
Makoto Nagata
Keyword(s):  
Integrated Circuits ◽  
Metal Layer ◽  
Three Dimensional ◽  
Chip Thickness ◽  
Power Delivery ◽  
Silicon Structure ◽  
Metal Insulator ◽  
3D Ics ◽  
Power Delivery Network ◽  
Global Power

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method

2009 ◽  
Author(s):  
Je-Hyoung Park ◽  
Ali Shakouri ◽  
Sung-Mo Kang
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Computation Time ◽  
Maximum Error ◽  
3D Ic ◽  
Additional Advantage ◽  
3D Ics ◽  
Ic Technology ◽  
Power Blurring

CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

High-Density Large-Area-Array Interconnects Formed by Low-Temperature Cu/Sn–Cu Bonding for Three-Dimensional Integrated Circuits

2012 ◽  
Vol 59 (7) ◽  
pp. 1941-1947 ◽  
Author(s):  
M. R. Lueck ◽  
J. D. Reed ◽  
C. W. Gregory ◽  
A. Huffman ◽  
J. M. Lannon ◽  
...  
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Three Dimensional ◽  
High Density ◽  
Large Area ◽  
Area Array ◽  
Cu Bonding
Sign in / Sign up

Export Citation Format

Share Document