Fabrication of Amorphous Si Thin-Film Transistors on an Engineered Parylene Template Using a Direct Separation Process

2008 ◽  
Vol 11 (1) ◽  
pp. J4
Author(s):  
C. C. Chiang ◽  
D. S. Wuu ◽  
Y. P. Chen ◽  
T. H. Jaw ◽  
R. H. Horng
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Separation Process ◽  
Direct Separation ◽  
Amorphous Si ◽  
Si Thin Film

Fabrication of Flexible Amorphous-Si Thin-Film Solar Cells on a Parylene Template Using a Direct Separation Process

2011 ◽  
Vol 58 (5) ◽  
pp. 1433-1439 ◽  
Author(s):  
Shih-Yung Lo ◽  
Dong-Sing Wuu ◽  
Chia-Hao Chang ◽  
Chao-Chun Wang ◽  
Shui-Yang Lien ◽  
...  
Keyword(s):  
Thin Film ◽  
Solar Cells ◽  
Separation Process ◽  
Thin Film Solar Cells ◽  
Direct Separation ◽  
Amorphous Si ◽  
Si Thin Film

Application of Self-Aligned Amorphous SI Thin-Film Transistors

1999 ◽  
Vol 557 ◽  
Author(s):  
J.P. Lu ◽  
P. Mei ◽  
C. Chua ◽  
J. Ho ◽  
Y. Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
New Technology ◽  
Channel Length ◽  
Shift Register ◽  
Flat Panel Displays ◽  
Flat Panel ◽  
Amorphous Si ◽  
Si Thin Film ◽  
Dynamic Shift

AbstractWe have successfully used self-aligned Amorphous Si Thin-Film Transistors, fabricated by a laser doping/annealing process, to construct dynamic shift register circuits, which can be used as gate-line drivers or in other peripheral circuits for flat-panel displays and imagers. Taking advantage of easily scaling down the TFT channel length in a self-aligned process, much higher circuit speeds can be achieved compared to that of circuits using conventional TFTs. We have successfully demonstrated a four-phase dynamic shift register, operating at a clock speed higher that 250 kHz (1 μs for each clock phase) built on 3 μm channel length TFTs. This new technology opens up possibilities for integrating peripheral circuits in flat-panel displays and imagers based on a-Si TFTs.

Why SiNx:H is the Preferred Gate Dielectric for Amorphous Si Thin Film Transistors (TFTS) and SiO2 is the Preferred Gate Dielectric for Polycrystalline Si TFTs

1999 ◽  
Vol 558 ◽  
Author(s):  
Gerald Lucovsky ◽  
J.C. Phillips
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Defect Density ◽  
Device Optimization ◽  
Constraint Theory ◽  
Dielectric Interfaces ◽  
Amorphous Si ◽  
Si Thin Film

ABSTRACTConstraint theory developed for bulk glasses and recently applied to thin films and single crystalline Si (C-Si) dielectric interfaces is extended in this paper to a-Si:H and polycrystalline-Si (poly-Si) dielectric interfaces in TFTs where it provides guidelines for device optimization. The constraining effects of network bonding forces are a linear function of the average bonding coordination, Nav. Nav ∼ 3 separates low-defect density networks as in Si02 (Nav =2.67), from highly-defective networks such as non-hydrogenated Si3N4 (Nay = 3.43). Nay ∼ 3 also separates device-quality from highly-defective Si-dielectric interfaces. These criteria are applied to Si-Si02 and Si-SiNx:H interfaces that are integral components of TFT devices.

A New Poly-Si Thin Film Transistors with Partial Amorphous Si Channel

1998 ◽  
Vol 37 (Part 1, No. 4A) ◽  
pp. 1727-1729
Author(s):  
Kwon-Young Choi ◽  
Kee-Chan Park ◽  
Hyoung-Bae Choi ◽  
Min-Koo Han
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Amorphous Si ◽  
Si Thin Film

The effect of lead impurity on amorphous Si thin film transistors

1989 ◽  
Vol 113 (1) ◽  
pp. K147-K148
Author(s):  
N. M. Ficza ◽  
A. L. Toth
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Amorphous Si ◽  
Si Thin Film

The impact of self-aligned amorphous Si thin film transistors on imager array applications

2000 ◽  
Vol 266-269 ◽  
pp. 1294-1298 ◽  
Author(s):  
J.P Lu ◽  
P Mei ◽  
J Rahn ◽  
J Ho ◽  
Y Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Amorphous Si ◽  
The Impact ◽  
Si Thin Film
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