Effect of Poly Silicon Wettability on Polymeric Residue Contamination

2019 ◽  
Vol 11 (2) ◽  
pp. 455-461 ◽  
Author(s):  
Young-Jae Kang ◽  
Jin-Goo Park ◽  
Yi-Koan Hong ◽  
Sang-Yeob Han ◽  
Seong-Kyu Yun ◽  
...  
Keyword(s):  
Poly Silicon ◽  
Polymeric Residue

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Poly-Silicon TFT Annealing with XeCl Excimer Laser.

2000 ◽  
Vol 28 (1) ◽  
pp. 24-28 ◽  
Author(s):  
Junichi SHIDA ◽  
Naoyuki KOBAYASHI ◽  
Hideaki KUSAMA
Keyword(s):  
Excimer Laser ◽  
Poly Silicon ◽  
Xecl Excimer Laser

scholarly journals SiOxNy:B layers for ex-situ doping of hole-selective poly silicon contacts: A passivation study

2019 ◽  
Author(s):  
Audrey Morisset ◽  
Raphaël Cabal ◽  
Valentin Giglia ◽  
Bernadette Grange ◽  
José Alvarez ◽  
...  
Keyword(s):  
Ex Situ ◽  
Poly Silicon

FTIR based nondestructive method for metrology of depths in poly silicon-filled trenches

2003 ◽  
Author(s):  
Shoaib H. Zaidi ◽  
George Stojakovic ◽  
Alois Gutmann ◽  
Cornel Bozdog ◽  
Ulrich Mantz ◽  
...  
Keyword(s):  
Nondestructive Method ◽  
Poly Silicon

scholarly journals Improve the Performance of SONOS Type UV TD Sensors Using IOHAOS with Enhanced UV Transparency ITO Gate

Coatings ◽  
2021 ◽  
Vol 11 (4) ◽  
pp. 408
Author(s):  
Wen-Ching Hsieh ◽  
Fun-Cheng Jong ◽  
Wei-Ting Tseng
Keyword(s):  
Aluminum Oxide ◽  
Threshold Voltage ◽  
Indium Tin Oxide ◽  
Silicon Oxide ◽  
Poly Silicon ◽  
Ito Film ◽  
Post Annealing ◽  
Response Performance ◽  
Fading Rate ◽  
Silicon Device

This research demonstrates that an indium tin oxide–silicon oxide–hafnium aluminum oxide‒silicon oxide–silicon device with enhanced UV transparency ITO gate (hereafter E-IOHAOS) can greatly increase the sensing response performance of a SONOS type ultraviolet radiation total dose (hereafter UV TD) sensor. Post annealing process is used to optimize UV optical transmission and electrical resistivity characterization in ITO film. Via nano-columns (NCols) crystalline transformation of ITO film, UV transparency of ITO film can be enhanced. UV radiation causes the threshold voltage VT of the E-IOHAOS device to increase, and the increase of the VT of E-IOHAOS device is also related to the UV TD. The experimental results show that under UV TD irradiation of 100 mW·s/cm2, ultraviolet light can change the threshold voltage VT of E-IOHAOS to 12.5 V. Moreover, the VT fading rate of ten-years retention on E-IOHAOS is below 10%. The VT change of E-IOHAOS is almost 1.25 times that of poly silicon–aluminum oxide–hafnium aluminum oxide–silicon oxide–silicon with poly silicon gate device (hereafter SAHAOS). The sensing response performance of an E-IOHAOS UV TD sensor is greatly improved by annealed ITO gate.

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